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DMA Memory Increment mode overflow

Question asked by stella.fausto.001 on Mar 9, 2016
Latest reply on Mar 9, 2016 by stella.fausto.001
Hi,
I am using the DMA for transfer data from ADC converter to external memory RAM.
The DMA is configured in incremental mode so every time that I read data from ADC converter they are stored in a different memory location.

I try to be clear:
-I read 16 bit of data from the data registre of ADC converter
-i ask the DMA to transfer data  to the RAM memory
-I increment the DMA memory pointer of 2 position (each position represent a 8 bit memory register)

All works fine but after writing 2^17 samples , the DMA start writing again from his original value.
I haven't find anything in the datasheet about this limitation, anybody know about some sort of shadow register ?

Thanks a lot for the help.

DMA2_Stream0->CR&=~(7<<25);
DMA2_Stream0->CR|=(0<<25);
DMA2_Stream1->CR&=~(7<<25);
DMA2_Stream1->CR|=(2<<25);
DMA2_Stream2->CR&=~(7<<25);
DMA2_Stream2->CR|=(1<<25);
 
 
DMA2_Stream0->CR|=(1<<13);
DMA2_Stream0->CR|=(1<<10);
 
DMA2_Stream1->CR|=(1<<13);
DMA2_Stream1->CR|=(1<<10);
 
DMA2_Stream2->CR|=(1<<13);
DMA2_Stream2->CR|=(1<<10);
 
 
DMA2_Stream0->CR&=~(3<<11);
DMA2_Stream0->CR|=(1<<11); //peripheral data syze imposto a half word(16bit)
 
DMA2_Stream1->CR&=~(3<<11);
DMA2_Stream1->CR|=(1<<11); //peripheral data syze imposto a half word(16bit)
 
DMA2_Stream2->CR&=~(3<<11);
DMA2_Stream2->CR|=(1<<11); //peripheral data syze imposto a half word(16bit)
 
DMA2_Stream0->CR|=(0<<6);// imposto peripheral  to memory transfer
DMA2_Stream1->CR|=(0<<6);// imposto peripheral  to memory transfer
DMA2_Stream2->CR|=(0<<6);// imposto peripheral  to memory transfer 
 
 
DMA2_Stream0->PAR= (uint32_t)( &(ADC1->DR));
DMA2_Stream1->PAR= (uint32_t)( &(ADC3->DR));
DMA2_Stream2->PAR= (uint32_t)( &(ADC2->DR));
 
DMA2_Stream0->M0AR=INDIRIZZO_SDRAM_ADC1;
DMA2_Stream1->M0AR=INDIRIZZO_SDRAM_ADC3;
DMA2_Stream2->M0AR=INDIRIZZO_SDRAM_ADC2;
 
DMA2_Stream0->CR|=(1<<5);
DMA2_Stream1->CR|=(1<<5);
DMA2_Stream2->CR|=(1<<5);
 
 
DMA2_Stream0->CR|=1; //abilito stream 0
DMA2_Stream1->CR|=1; //abilito stream 1
DMA2_Stream2->CR|=1; //abilito stream 2

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