AnsweredAssumed Answered

Need help for STM32F103RD PLL setup

Question asked by on Mar 6, 2016
Latest reply on Mar 11, 2016 by
Hi everyone! i got some prob when i trying to setup PLL run at full speed 72MHz. Here is my code
01.RCC_CR_bit.HSEON = 1;              //enable HSE
02.while(!RCC_CR_bit.HSERDY);         //wait for HSE ready
04.RCC_CFGR_bit.PLLSRC = 1;           //PLL source = HSE (0:HSI/2, 1:HSE)
05.RCC_CFGR_bit.PLLXTPRE = 1;         //PLL = HSE/2 = 8MHz (0:not div, 1:div by 2)
06.RCC_CFGR_bit.PLLMUL = 0x07;        //PLL = HSE x 9 = 72MHz (<=72MHz)
07.RCC_CFGR_bit.USBPRE = 0;           //USB = PLL/1.5 = 48 MHz (0:div by 1.5, 1:not div)
08.RCC_CFGR_bit.PPRE1 = 0x05;         //HCLK prescaler (<=36MHz)
09.RCC_CR_bit.PLLON = 1;              //enable PLL
10.while(!RCC_CR_bit.PLLRDY);         //wait for PLL ready
13.RCC_CFGR_bit.SW = 0x02;            //select system clock (HSI = 00, HSE = 01, PLL = 10)
14.while(!(RCC_CFGR_bit.SWS==0x02));  //wait for system clock turn into PLL (HSI = 00, HSE = 01, PLL = 10)
15.RCC_CR_bit.HSION=0;                //turn off HSI to save power
18.RCC_AHBENR = 0;                    //bit => 10:SDIO, 8:FSMC, 6:CRC, 4:FLITF, 2:SRAM, 1:DMA2, 0:DMA1
19.RCC_APB2ENR = 0;                   //bit => 21:TIM11, 20:TIM10, 19:TIM9, 15:ADC3, 14:USART1, 13:TIM8, 12:SPI1, 11:TIM1, 10:ADC2, 9:ADC1, 8:IOPG, 7:IOPF, 6:IOPE, 5:IOPD, 4:IOPC, 3:IOPB, 2:IOPA, 0:AFIO
20.RCC_APB1ENR = 0;                   //bit =>29:DAC, 28:PWR, 27:BKP, 25:CAN, 23:USB, 22:I2C2, 21:I2C1, 20:UART5,19:UART4, 18:USART3, 17:USART2, 15:SPI3, 14:SPI2, 11:WWDG,8:TIM14, 7:TIM13, 6:TIM12, 5:4:TIM6, 3:TIM5, 2:TIM4, 1:TIM3, 0:TIM2
Im using xtal 16MHz and debugger show that my program stuck at switching system clock source to PLL. when I lower the PLLMUL my chip work again. I think I misunderstood something when reading manual.
Another question: I read some other code in which they using &=, |=,... to set or reset a bit in a register. Does it better than using <register_name>.<bit_name> = 0 (or =1)?
Thanks for reading :")