AnsweredAssumed Answered

stm3f373 clock and flash latency setting

Question asked by choi.gazam on Mar 4, 2016
Latest reply on Mar 4, 2016 by Amel N

I worked with stm32f373.
To reduce power consumption I change the Hclk to 24Mhz and 48Mhz System clock.
(use AHB prescaler to /2)
But I confused by flash setting.
reference manual said that the latency is

000: Zero wait state, if 0 < SYSCLK≤ 24 MHz
001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
010: Two wait sates, if 48 < SYSCLK ≤ 72 MHz

but the st library source code said that the latency is choosed by Hclk  not system clock
what is correct?

and what should I consider when the sys clk different with Hclk ?