AnsweredAssumed Answered

Need help on STM32F207 errata position 2.3.2 (I2C)

Question asked by Mr_M_from_G on Feb 29, 2016
Latest reply on Mar 2, 2016 by Mr_M_from_G
 we are using STM32F207ZGT6J with rev code X and we are in trouble with I2C communication. It runs fine for hours with tens of messages per second and then suddenly it doesn't generate a start condition anymore. After hours of testing I finally came to take a look at errata sheet and found this:
2.3.2  Start cannot be generated after a misplaced Stop


If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot generate a Start anymore.


In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits + acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it, but they are not supported by the I²C peripheral.

A software workaround consists in asserting the software reset using the SWRST bit in the I2C_CR1 control register.
For me there are a number of questions on this text:
- How can there be a misplaced stop condition in master mode? Stop conditions are placed by hardware so they should be in place always or never. (We have a single master system with this F207 being the master)
- How can I determine that this situation occured?
- What exactly is reset when using SWRST? Is it the same effect as using RCC_APB1RSTR_I2C1RST ?
- Are there more recent revisions that don't have this error? Or other STM32-controllers that are pin compatible to STM32F207?

Thanks a lot for any help