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I2C in STM32L4/STM32F7: Can Master enforce SCLs in SDA bus blocking situation?

Question asked by bil.til on Feb 28, 2016
I just had a more careful look at the new I2C module for STM32L4 (I think identical also in the new STM32F7):
In STM32F4 I always had the problem (STM32F4 being bus master), that a "stupid slave without timeout functionality" by some accident could keep the SDA line in dominant state (0V / Low) - thus then inhibiting the STM32 start condition, and so in fact blocking the bus. This could be only resolved by manully pushing out 9 SCL clock pulses (by switching SCL GPIO back to non-alternative function and doing this "manually"). This is very disturbing, especially in state machine programming, where you do not want to insert any delay loops in the code.

In STM32L4 I2C module there seem to be 2 interesting new bits:
ADDRCF - this somehow seems to enforce the Start condition (or does it only reset the START bit? - this is not completely clear from the docu...).
RD_WRN - this somehow seems to enforce the Read or Write direction for the master ... (in STM32F4 this did not exist - I think there the Read/Write was selected automatically depending on the ADDR Byte low bit ...).

... maybe it is possible with these two bits to resolve such an SDA Low block condition and enforce 9 SCL pulses from I2C module by reading a data byte, even if the start condition fails? Anybody any idea?