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STM32F103 watchdog problem

Question asked by FD on Feb 24, 2016
Latest reply on Feb 25, 2016 by FD
Hello together,

I have some problems with the IWDG of the STM32F103RBT6. I hope you can help me.
The initialization:
  // Clear reset flags
  if( RCC_CSR & (1 << 29))
  {
    RCC_CSR |= (1<<24);
  }
    
  /* Configure the watchdog */
  IWDG_KR  = 0x5555; /* Configuration access enabled */
  IWDG_PR  = 0x0002; /* Prescaler code 2: divider /16 */
  IWDG_KR  = 0x5555;
  IWDG_RLR = 0x04E2; /* 0x04E2 = 1250, f=40kHz, -> 1250 * 16 / 40000 = 500ms*/
  IWDG_KR  = 0xCCCC;

The IWDG is cyclic triggered by:
   IWDG_KR = 0xAAAA;

If the program runs into an infinite loop for testing the "IWDGRSTF" flag of the RCC_CSR register is set. But then the watchdog does not reset the controller, it still hungs in the infinite loop.
The both bits of the status register "IWDG_SR" (RVU, PVU) are not set the whole time.
Do you have any idea what I'm doing wrong? Thank you!

Best regards from Germany
FD

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