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SPI aberration (STM32F401VC)

Question asked by deering.paul on Feb 7, 2016
Latest reply on Feb 7, 2016 by Clive One
Hi all,

I have an issue with SPI on the STM32F401VC microcontroller.  What seems to be the problem is that the SPI device (SPI1) doesn't seem to drive the completion flags correctly on the hardware.  For example, I have setup SPI1 to transmit a single 8 bit test value (see attached hardware trace), and the BSY and RXNE are reporting that the transfer has completed and the byte received before it should be (see CS on the trace).  CS is being driven active before the SPI operation, and then immediately after the SPI transfer has completed.

As can be seen in the trace, CS is being driven to DISABLE before the final clock cycle has completed, which shouldn't occur as the SPI transmit function is actively polling BSY and RXNE before CS is being set to DISABLE.

Basically, the operation is to:
     (1)  Drive CS low
     (2)  Wait for TXE to become set
     (3)  Write the byte to the data register
     (4)  Wait for RXNE to become set
     (5)  Retrieve the clocked in byte from the data register
     (6)  Wait for the BSY flag to become reset
     (7)  Drive CS high  

Any ideas?

 

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