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SPI Data Register problem in Slave!

Question asked by Blade87 on Jan 23, 2016
Latest reply on Jan 24, 2016 by Blade87
Hello everyone
Recently I connect two STM32F401RE Nucleo with SPI interface.The configurations for master and slave are full duplex, CLK/256, 16-bit, Mode 0 and MSB first. When master produce the clock, data (0x0080) from slave will send out to master, but after some transitions slave data will slightly shift to the left(0x0100) and again after some transitions data will become 0x0200 and so on. I disconnect MOSI pin and connect Slave MOSI pin to gnd and test the data, it happend again. I used logic analyzer and Keil debugger, both confirmed that the data has been changed. Something will change the Slave SPI Data register and I can't completely clear it before sending the rest of data. Did anyone experience same problem?