AnsweredAssumed Answered

STMF030 ADC

Question asked by Johnson.Mark.001 on Jan 18, 2016
Latest reply on Jan 18, 2016 by Clive One
I am writing code for ADC in Assembly. Can anyone confirm or share an experience if there is a minimum latency or delay requirement after the ADC Cal routine is finished before ADEN bit can be set? I find I need a minimum 125nS delay after cal routine before I can set ADEN bit to 1 and allow for ADRDY bit be set.

All provided examples are in C and each ADC configuration example program is executed with a function providing some amount of latency between called functions and a area "For robust implementation, add here time-out management."

I'm polling the ADCAL bit and finding I need 5 cycles (125nS) of delay before I can set the ADEN. If I do not insert this delay, program will loop and never receive an ADRDY.



        STR R0,[R1] ;MOVE ADC_CFGR2 DATA TO SELECT PCLK/4 ( SYS CLK = 40MHz/4 = ADC CLK = 10MHz)
        LDR R1,=0x40012408 ;MOVE ADC_CR ADDRESS TO R1
        LDR R0,=2_10000000000000000000000000000000 ;ADCAL = 1 DATA
        STR R0,[R1] ;MOVE ADC_CR DATA TO SET ADCAL = 1

ADCE10

        LDR R0,[R1] ;MOVE ADC_CR LOCATION DATA TO R0
        LSRS R0,#32 ;MOVE ADCAL BIT #31 TO CARRY
        BCS ADCE10 ;WAIT UNTIL ADCAL = 0 TO CONTINUE DOWN
               
         LDR R2,=1 ;MINIMUM DELAY ROUTINE I ADDED BEFORE I SET ADEN
CDLY          
        SUBS R2,#1
        BNE CDLY

        LDR R0,=2_00000000000000000000000000000001 ;ADEN = 1 DATA
        STR R0,[R1] ;MOVE ADC_CR DATA TO SET ADEN = 1
        LDR R1,=0x40012400 ;MOVE ADC_ISR ADDRESS TO R1                         

ADR0
        LDR R0,[R1] ;MOVE ADC_ISR DATA TO R0
        LSRS R0,#1 ;MOVE ADRDY BIT TO CARRY
        BCC ADR0 ;WAIT UNTIL ADRDY = 1 TO CONTINUE DOWN, CODE WILL LOOP HERE WITHOUT ADDED CDLY

Outcomes