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Precisely timed latching

Question asked by Luke on Jan 17, 2016
Latest reply on Jan 18, 2016 by Clive One
So I am running and STM32F0 at 48Mhz with TIM1 clocked to an external clock source running at 24.576MHz. On GPIO-A is connected a bus synced to the external 24.576Mhz clock. At occasional intervals I want to latch a value on the bus based on a tick count on TIM1. Obviously since the timing requirements are very tight, the delays inherent in TIM1 and its CCs/DMA become very important. One approach I have thought about is using an OC on TIM1 that triggers a DMA transfer, however I have noted that timing may be difficult in this case as there is a noticeable delay before the transfer happens. Another approach might be using an external latch and generating a latch pulse on a TIM1 OC, although I believe there are going to be delays associated with OCs that will probably be relevant here also. Is there a way to latch a GPIO at a precise clock tick and then immediately stop latching to save IDR state?

I suppose my main issue currently is being able to ensure I can latch a value on the port with precise enough timing that it matches up with the desired tick on the 24.576MHz clock. Perhaps there is a way to adjust the OC timing with a short delay to make sure it aligns with the incoming clock signal and latches the correct value on the port (i.e. delay until the next pulse and set the OC a pulse earlier)?

I also need to occasionally put data on the bus for a single tick and then return the port to a high impedance state. I'm not sure this is possible with the MCU itself, although I can attach an external latch, put a value on it then generate a pulse to open the latch which will return to high impedance state once the line returns low. Obviously the pulse timing is very important here, and would need to output a one tick pulse to the latch from TIM1 OC.

Perhaps there is no practical way to get this kind of strict timing at the given core clock speed and I need to add some external components to calibrate the delay, then trigger pulses a tick earlier than required? Are the TIM1/OC delays predictable enough to ensure such a solution would work?

Thanks in advance for any comments

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