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NDTR Register is Zero but no Interrupt set

Question asked by markus.s on Jan 7, 2016
Latest reply on Jan 7, 2016 by markus.s
Hello all,
I obsarvate an problem with the DMA in STM32F2.
I am using the STM322xG-Eval Board for the development.
The firmware streams data from SRAM to I²S by DMA. I also use in the same firmware FreeRTOS.
After a couple of time (sometimes after few Minutes and sometimes after over an hour) the transmission stops.
I see in the DMA registers that the NDTR register is zero but the TCIF flag is not set and so the interrupt service routine is not called.
Does anyone has an idea what this behaviour could cause?
HW_DMA1b.jpg
HW_DMA_CR.jpg

HD_Regs.jpg

This is the DMA and I²S configuration:
01.DMA Config
02.{
03./* Set the parameters to be configured */
04.  DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL; 
05.  DMA_InitStructure.DMA_PeripheralBaseAddr = CODEC_I2S_ADDRESS;
06.  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0;      /* This field will be configured in play function */
07.  DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
08.  DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;      /* This field will be configured in play function */
09.  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
10.  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
11.  DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
12.  DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE;
13. 
14.DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
15. 
16.DMA_InitStructure.DMA_Priority = DMA_Priority_High;
17.  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;        
18.  DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
19.  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
20.  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; 
21.  DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); 
22. 
23.DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE);
24.DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE);
25.DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
26.SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
27.   
28.  /* I2S DMA IRQ Channel configuration */
29.  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
30.  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
31.  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
32.  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
33.  NVIC_Init(&NVIC_InitStructure);
34.}
35. 
36.I²S config
37.{
38.I2S_InitTypeDef I2S_InitStructure;
39. 
40.  /* Enable the CODEC_I2S peripheral clock */
41.  RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
42. 
43.  /* CODEC_I2S peripheral configuration */
44.  SPI_I2S_DeInit(CODEC_I2S);
45.  I2S_InitStructure.I2S_AudioFreq = AudioFreq;
46.  I2S_InitStructure.I2S_Standard = I2S_STANDARD;
47.  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
48.  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
49.  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
50.I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
51.I2S_Init(CODEC_I2S, &I2S_InitStructure);
52.}


Regards, Markus

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