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[Solved] Sync TIM2 & TIM5 on capture/compare event

Question asked by Vinci on Dec 22, 2015
Latest reply on Feb 28, 2018 by gudgel.bob
Hello

I can't seem to get a timer sync on a capture and compare event working, but let's build up a little. According to the internal trigger connection of timers 2-5 it's possible to link #5 as slave with #2 as master by the internal connection ITR0.

Doing that with the HAL libraries is rather simple:
/* Master */
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;
HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);
 
/* Slave */
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_COMBINED_RESETTRIGGER;
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
HAL_TIM_SlaveConfigSynchronization(&htim5, &sSlaveConfig);

This works like a charm. Now the problem is that timer 2 (master) triggers a rather important measurement for a control loop about 2ms into it's own 10ms period. The measurement is completed on the capture and compare event of channel 3. Since waiting another ~8ms for the update event to occur is bad for the control loop I'd rather trigger my slave timer update with capture and compare event itself.

According to the datasheet thats possible:
MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)


So I simply changed my master timer initialization to:
sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC3REF;

But that didn't work. In fact now the slave doesn't get triggered at all. The library functions should work though... because all the right bits seem to get set. Am I missing something trivial? Doesn't OC3REF mean what I think it does?


/edit
Ok, apparently OCxREF is not what I thought it to be...
Using "OC1" as output trigger now works.

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