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Cortex-M0 ADC Latency STM32F030

Question asked by Johnson.Mark.001 on Dec 21, 2015
Latest reply on Dec 21, 2015 by wolff.roger
Clarification needed... When does the ADC EOC Flag get set? Before or after the ADC_DR write latency?

ADC clock settings:
Pclk/4 = 40MHz/4=10MHz(ADC_CLK 100nS). Write latency spec: 8.5 fpclk typ. (8.5 * 100ns = 850ns latency).

RM0360 Description pg. 195
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.