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Same calculation time in both 36MHz and 64MHz

Question asked by Nima on Dec 15, 2015
Latest reply on Dec 15, 2015 by Clive One
Hi everybody
I am trying to implement some mathmatic calculations in STM32F103.
I use HSI and PLL to provide 64MHz and 36MHz clock, considering Flash Wait State and enabling Prefetch Buffer.
 I expect that the calculation time in 64MHz should be faster that 36MHz. As I checked, in both cases, the calculation time is almost same (e.g. 110 usec).
For your information, I used the Timer counter value (e.g. Timer 1) in debug mode (DBGMCU_TIM1_STOP enabled) to calculate the time required for calculation processes.  I use the following method to find the calcuation time:
I inserted one break point exactly before first line of mathematics processes and one break point exactly after them.
When the execution of my code is stopped at first break point I record the Timer 1 counter value (e.g. C1=1000).
Then in second break point, I again record the counter value (e.g. C2=8000).
Then I calculate the time by:
(C2-C1)*(1+Tim1Prescaler)/Tim1ClockFrequency=(7000*(1+0)/64MHz)=109 usec.

Each instruction need some clock cycles to do calculations. Therefore, I expect that if the frequency of Clock is increased, then that instruction will be calculated faster. Am I right?

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