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HSE ext. clock with PLL

Question asked by schmitt.frank on Dec 8, 2015
Latest reply on Dec 9, 2015 by Amel N
Hello,

im using a STM32f103 with a external digital clock of 10MHz. By the PLL it was set up to 30MHz with fit to our application.

I used the std. perherals library to configure the clock. I adapted the function:

SetSysClockTo36()
I changed the PLL configuration to get a SYSCLK of 30MHz
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
//    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);

I did not activate the bypass bit in the RCC_CR register.
Could this cause a problem?

Thanks
Frank

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