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SPC560Bx ECC Testing

Question asked by wallis.kevin on Sep 29, 2015
Latest reply on Apr 7, 2016 by mason.william
We're trying to write a startup test for ECC detection using the EEGR register (table 524 of the reference manual RM0037). However it appears as if once a data inversion is forced (resulting in an IVOR 2 exception) it continues to occur following return from interrupt (rfi) regardless of ESR (and other ECSM register) clearing.
Is this expected behaviour, and/or is there a recommended sequence to recover from an EEGR-injected ECC error?