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STM32F334 HRTIM WITH BAD BEHAVIOR

Question asked by mendes.ari.001 on Nov 26, 2015
Latest reply on Nov 2, 2017 by jose.luu
Hi,
I'm experiencing a very bad behavior of HRTIM.
if output set register is set on Period and output reset register is reset on CMP1.
if CMP1 = 0x20, the PWM output is a narrow pulse as expected. but if the CMP1 < 0x20 the output go to active state. The duty cycle goes to near zero to 100%. This is very bad!

the section 10.3.6 of the RM0364 states that:
if the set and reset events are generated within same HRTIM clock period, the reset event has the highest priority and the set event is ignored. But what is happening is the opposite of it.
Someone else noticed this issue before or I'm missing something?

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