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stm32f401re nucleo: PLL configuration

Question asked by engkyr on Nov 26, 2015
Latest reply on Nov 26, 2015 by engkyr
Hello everybody!


I'm trying to configure the main PLL to generate the max clock frequency (84 MHz on this board), and I'm using the HSI as PLL source.


I made some test:
- test1: HCLK=70 MHz
M=16
N=140
P=2
AHB_PR=1
APB1_PR=2
APB2_PR=1


As soon as I set the PLL output as HCLK, the uC stops working.
I mean:
- no blinking led
- random value on general purpose register


I made some test:
- test2: HCLK=35 MHz
M=16
N=140
P=2
AHB_PR=2
APB1_PR=2
APB2_PR=1
The uC works normally.


I'm missing some configuration (i.e. ART?), or the problem is the HSI and his accuracy?
Could someone help me to figure it out? Thanks!


Regards

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