The serial bit rate is derived by dividing down the input clock PCLK. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in SSP_PR. The clock
is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value
programmed in SSP_CR0.
The frequency of the output signal bit clock SCLK is defined below:
fSCLK=fPCLK / (CPSDVR + (1+SCR))
For example, if PCLK is 3.6864MHz, and CPSDVSR = 2, then SCLK has a frequency range
from 7.2kHz to 1.8432MHz.
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