I am trying to understand a few things connected with the Ethernet peripheral (more precisely – its dedicated DMA) which can be found in some STM32F4 devices. In this post I am referring to the STM32F429/439 Reference Manual.
The reference manual describes two basic structures which are formed by the descriptors – they are the chain structure and the ring structure. In the case of the ring structure everything seems clear to me. But I have 2 questions connected with the chain structure and both of them:
1. In the chain structure – I have seen some drivers in which the chain structure is formed and the last descriptor points to the first one. My question is (as an example – the case of transmit descriptors): could the last descriptor, instead of pointing to the first descriptor, have TER (Transmit end of ring) bit in the TDES0 (Transmit descriptor Word0) set?
2. Is it possible to mix both ideas (ring & chain structures)? As an example – the case of transmit descriptors: some descriptors would have TCH (Second address chained) bit of the TDES0 set and point to the next descriptor as in the “pure” chain mode. Others would have the TCH bit reset and point to 2 buffers each; then the next descriptor would be obtained as in the “pure” ring mode – from the DSL (Descriptor skip length) field in the Ethernet DMA bus mode register (ETH_DMABMR). The last descriptor would either point to the first descriptor or have TER (Transmit end of ring) bit in the TDES0 (Transmit descriptor Word0) set.