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Using CLI

Question asked by sawicki.aleksander on Nov 5, 2015
Latest reply on Nov 5, 2015 by Nesrine M
Hello!
I have a problem when i try to use CLI.

When I open and run it, I have list of instruction and  system is waiting for any key
- Option bytes commands ------------------------------------------------
-rOB      Display all option bytes
-OB       Configure the option bytes
          Syntax: -OB [RDP=<Level>]          [BOR_LEV=<Level>]
                      [WWDG_SW=<Value>]      [IWDG_SW=<Value>]
                      [IWDG_STOP=<Value>]    [IWDG_STDBY=<Value>]
                      [nRST_STOP=<Value>]    [nRST_STDBY=<Value>]
                      [IWDG_ULP=<Value>]     [FZ_IWDG_STOP=<Value>]
                      [nBOOT_SEL=<Value>]    [FZ_IWDG_STDBY=<Value>]
                      [nRST_SHDW=<Value>]    [PCROP_RDP=<Value>]
                      [nBFB2=<Value>]        [BFB2=<Value>]
                      [nBoot1=<Value>]       [Boot1=<Value>]
                      [nBoot0=<Value>]       [nBoot0_SW_Cfg=<Value>]
                      [VDDA=<Value>]         [SDADC12_VDD=<Value>]
                      [DB1M=<Value>]         [DUALBANK=<Value>]
                      [nDBANK=<Value>]       [BOOT0_nSW_Config=<Value>]
                      [Data0=<Value>]        [Data1=<Value>]
                      [nSRAM_Parity=<Value>] [SRAM2_RST=<Value>]
                      [SRAM2_PE=<Value>]     [SPRMOD=<Value>]
                      [PCROPA_STRT=<Value>]  [PCROPA_END=<Value>]
                      [PCROPB_STRT=<Value>]  [PCROPB_END=<Value>]
                      [WRP=<Value>]          [WRP2=<Value>]
                      [WRP3=<Value>]         [WRP4=<Value>]
                      [WRP1A_STRT=<Value>]   [WRP1A_END=<Value>]
                      [WRP1B_STRT=<Value>]   [WRP1B_END=<Value>]
                      [WRP2A_STRT=<Value>]   [WRP2A_END=<Value>]
                      [WRP2B_STRT=<Value>]   [WRP2B_END=<Value>]
 
Press any key to continue
as
And when I press any key a console dissapear!
Any suggestion?

When I run program in cmd.

Press any key to continue
as
   RDP=<Level>: Set the flash memory read protection level
      0: Protection disabled             1: Protection enabled
      2: Protection enabled(debug & boot in SRAM features are DISABLED)
 
   BOR_LEV=<Level>: Set the Brownout Reset threshold level
      For STM32 L1:
               0: BOR OFF,1.45 to 1.55 V voltage range
               1: 1.69 to 1.8 V voltage range
               2: 1.94 to 2.1 V voltage range
               3: 2.3 to 2.49 V voltage range
               4: 2.54 to 2.74V voltage range
               5: 2.77 to 3.0 V voltage range
      For STM32 F2, STM32 F4 and and STM32 L4
               0: BOR OFF, 1.8 to 2.10 V voltage range
               1: 2.10 to 2.40 V voltage range
               2: 2.40 to 2.70 V voltage range
               3: 2.70 to 3.60 V voltage range
 
   WWDG_SW=<Value>: <Value> should be 0/1
      0: Hardware window watchdog         1: Software window watchdog
 
   IWDG_SW=<Value>: <Value> should be 0/1
      0: Hardware independent watchdog    1: Software independent watchdog
 
   IWDG_ULP=<Value>: <Value> should be 0/1
      0: IWDG clock can't be disabled
      1: IWDG clock can be disabled by the RCC when entering low power modes
 
   IWDG_STOP=<Value>: <Value> should be 0/1
      0: Independent watchdog counter is frozen in Stop mode
      1: Independent watchdog counter is running in Stop mode
 
   IWDG_STDBY=<Value>: <Value> should be 0/1
      0: Independent watchdog counter is frozen in Standby mode
      1: Independent watchdog counter is running in Standby mode
 
   FZ_IWDG_STOP=<Value>: <Value> should be 0/1
      0: Freeze IWDG counter in STOP mode
      1: IWDG counter active in STOP mode
 
   FZ_IWDG_STDBY=<Value>: <Value> should be 0/1
      0: Freeze IWDG counter in STDBY mode
      1: IWDG counter active in STDBY mode
 
   nRST_STOP=<Value>: <Value> should be 0/1
      0: Reset generated when CPU enters Stop mode     1: No reset generated
 
   nRST_STDBY=<Value>: <Value> should be 0/1:
      0: Reset generated when CPU enters Standby mode  1: No reset generated
 
   nRST_SHDW=<Value>: <Value> should be 0/1
      0: Reset generated when entering Shutdown mode   1: No reset generated
 
   PCROP_RDP=<Value>: <Value> should be 0/1
      0: PCROP area not erased when RDP level decreased from 1 to 0
      1: PCROP area erased when RDP level decreased from 1 to 0=>full mass eras
 
 
   nBFB2=<Value>: <Value> should be 0/1
      0: Boot from flash bank 2 when boot pins set in "boot from user Flash"
      1: Boot from flash bank 1 when boot pins set in "boot from user Flash"
 
   BFB2=<Value>: <Value> should be 0/1
      0: Boot from flash bank 1 when boot pins set in"Boot from user Flash"
         (default)
      1: Boot from flash bank 2 when boot pins set in "Boot from user Flash"
 
   nBoot1=<Value>: <Value> should be 0/1
      With Input pad Boot0 (or Option bit nBoot0) selects the Boot Source
 
   nBoot0=<Value>: Value should be 0/1: Active only when Boot0_SW_Cfg is set
 
   nBoot0_SW_Cfg=<Value>: <Value> should be 0/1:
      0: Allows user to disable BOOT0 pin completely & use nBoot0 Option bit
      1: The BOOT0 is bonded to GPIO pin (PB8 on LQFP32 and smaller packages,
         PF11 for QFN32 and bigger packages)
 
   BOOT0_nSW_Config=<Value>: <Value> should be 0/1:
      0: boot0 taken from the option bit
      1: boot0 taken from the pad
 
   nDBOOT=<Value>: <Value> should be 0/1:
      0: Dual boot enabled
      1: Dual boot disabled
 
   nBOOT_SEL=<Value>: <Value> should be 0/1:
      0: BOOT0 taken from the pad
      1: BOOT0 taken from the nBOOT0 option bit
 
   VDDA=<Value>: <Value> should be 0/1:
      Selects the analogue monitoring on VDDA Power source
 
   SDADC12_VDD=<Value>: <Value> should be 0/1
      Slects analogue monitoring (comparison with Bgap 1.2V voltage)
      on SDADC12_VDD Power source
 
   Data0=<Value>: Set Data0 option byte.<Value> should be in [0..0xFF]
 
   Data1=<Value>: Set Data1 option byte.<Value> should be in [0..0xFF]
 
   BOOT_ADD0=<Value>: Value should be in [0..0xFFFF]
       Boot Address enable when Boot0=0
       BOOT_ADD0[15:0] correspond to address [29:14]
 
   BOOT_ADD1=<Value>: Value should be in [0..0xFFFF]
       Boot Address enable when Boot0=1
       BOOT_ADD1[15:0] correspond to address [29:14]
 
   nSRAM_Parity=<Value>: <Value> should be 0/1
       This bit allows the enable of the SRAM hardware parity check
       0: Parity check enabled           1: Parity check disabled
 
   SRAM2_RST=<Value>: <Value> should be 0/1
       This bit allows the enable of the SRAM2 erase on system reset
       0: SRAM2 erased when a system reset occurs
       1: SRAM2 is not erased when a system reset occurs
 
   SRAM2_PE=<Value>: <Value> should be 0/1
       This bit allows the enable of the SRAM2 hardware parity check
       0: SRAM2 parity check enable      1: SRAM2 parity check disable
 
   SPRMOD=<Value>: <Value> should be 0/1
       Selection of protection mode of nWPRi bits
       0: nWPRi bits used for sector i write protection
       1: nWPRi bits used for sector i PCROP protection
 
   PCROPA_STRT=<Value>:  <Value> should be in [0..0xFFFFFFFF]
       Read/Write Protection Start address for bank A.
       Note: PCROPA_STRT must be in the active zone of Bank A
       Note: PCROPA_STRT must be Double Word aligned
 
   PCROPA_END=<Value>:  <Value> should be in [0..0xFFFFFFFF]
       Read/Write Protection End address for bank A
       Note: PCROPA_END must be in the active zone of Bank A
       Note: PCROPA_END must be Double Word aligned
 
   PCROPB_STRT=<Value>:  <Value> should be in [0..0xFFFFFFFF]
       Read/Write Protection Start address for bank B
       Note: PCROPB_STRT must be in the active zone of Bank B
       Note: PCROPB_STRT must be Double Word aligned
 
   PCROPB_END=<Value>:  <Value> should be in [0..0xFFFFFFFF]
       Read/Write Protection End address for bank B
       Note: PCROPB_END must be in the active zone of Bank B
       Note: PCROPB_END must be Double Word aligned
 
   WRP=<Value>: Enables/Disables write protection of the flash sectors
       Each bit will Enable/Disable the write protection of one sector
       or more depending on the connected device
       For STM32 L1      => WRP[i] = 0 : Flash sector(s) is protected
       For other devices => WRP[i] = 1 : Flash sector(s) is protected
       For other devices => WRP[i] = 1 : Flash sector(s) is protected
       Note: <Value> should be in [0..0xFFFFFFFF]
 
   WRP2=<Value>: WRP2 is available only for STM32 L1 medium density
       plus, high density and high density plus devices to enable or
       disable the protection of Flash sectors from page 512 to 1023
       Note: <Value> should be in [0..0xFFFFFFFF]
 
   WRP3=<Value>: WRP3 is available only for STM32 L1 high density and
       high density plus devices to enable/disable the protection of
       Flash sectors from page 1024 to 1535
       Note: <Value> should be in [0..0xFFFFFFFF]
 
   WRP4=<Value>: WRP4 is available only on STM32 L1 high density plus
       devices to enable/disable the protection of flash
       sectors from sector 1536 to sector 2047
       Note: <Value> should be in [0..0xFFFFFFFF]
 
   WRP1A_STRT=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone A on Bank 1
       Note: WRP1A_STRT must be in the active zone of Bank 1
 
   WRP1A_END=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone A on Bank 1
       Note: WRP1A_END must be in the active zone of Bank 1
 
   WRP1B_STRT=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone B on Bank 1
         Note: WRP1B_STRT must be in the active zone of Bank 1
 
   WRP1B_END=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone B on Bank 1
       Note: WRP1B_END must be in the active zone of Bank 1
 
   WRP2A_STRT=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone A on Bank 2
       Note: WRP2A_STRT must be in the active zone of Bank 2
 
   WRP2A_END=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone A on Bank 2
       Note: WRP2A_END must be in the active zone of Bank 2
 
   WRP2B_STRT=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone B on Bank 2
       Note: WRP2B_STRT must be in the active zone of Bank 2
 
   WRP2B_END=<Value>: <Value> should be in [0..0xFF]
       Flash Page Index of Start Write Protection Zone B on Bank 2
       Note: WRP2B_END must be in the active zone of Bank 2
 
   DB1M=<Value>: <Value> should be 0/1
       Dual-Bank on 1MB Flash
 
   DUALBANK=<Value>: <Value> should be 0/1
       Dual-Bank on 512KB Flash or 256K Devices
       0: 512KB/256K Single Flash Bank
       1: 512KB/256K Dual-Bank Flash with contiguous addresses
 
   nDBANK=<Value>: <Value> should be 0/1
       Flash 256 bits mode
       0: The two 1MB banks are seen as a single bank with 256 bits
       1: The two 1MB banks are seen as a dual bank with 128 bits
 
   nDBOOT=<Value>: <Value> should be 0/1
       Dual Boot mode enable
       0: Dual Boot enabled. Boot always from ICP if boot address in flash
         (Dual bank Boot mode), or RAM if Boot address option in RAM
       1: Dual Boot disabled. Boot according to boot address option (Default)
 
------------------------------------------------------------------------
For more details, please refer to the Option Bytes section in the Flash
programming manual corresponding to your device available at www.st.com
------------------------------------------------------------------------
Note: All parameters should be in hexadecimal format
And program is quit.

OK i solved it :) 
if someone have similar doubt
ST-LINK_CLI -List



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