ST Community -
An application has the current design parameters for a Cortex M0 device STM32F030R8:
CLK: 20MHz external xtal on (PF0 & PF1 RCC OSC) internal PLL to 40MHz (25ns).
Regarding Timer 3, I want to create a delay (1-399) 25ns cycle time, in response to an external rising input edge coming into PA6. What is the preferred input channel (CHx) or ETR should be used to start the counter? I would then need to output the delayed edge on which one of the output channels? To achieve this function code should load the counter ARR or CRR to the delay time?
I realize there will be a latency but can tolerate a few cycles.Any expertise on the internal working of TIM3 to achieve this function is appreciated.