AnsweredAssumed Answered

PLL Settings

Question asked by qwer.asdf on Oct 23, 2015
Latest reply on Oct 25, 2015 by tjerneld.mikael
Hi, is there any difference how exactly I'm getting the desired clock speed on SYSCLK through PLL? For example, let's say I want to have 48MHz on SYSCLK on STM32F407, using a 8 MHz HSE and the PLL. One way of doing it would be this:

HSE = 8MHz
M = 8
N = 384
P = 8
Q = 8

Another way of doing it would this:

HSE = 8MHz
M = 4
N = 96
P = 4
Q = 4

So my question is: is one of these two ways better than the other (i.e. lower jitter, or lower power consumption), and why?

Thank you.