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STM32F7 HAL DMA cache coherence and DTCM RAM differentiation

Question asked by EvilMav on Oct 20, 2015
Latest reply on May 4, 2018 by Clive One
Hello Community!

I would like to know how, where, and on what conditions the DMA safety is ensured in STM32F7 HAL drivers and how DTCM is considered in them.

I've generated a Cube-Project with freeRTOS for SystemsWorkbench and use it as the basis. What struck my eye is that the link-script only has two sections: FLASH and RAM, RAM spanning both DTCM and normal ram blocks.

Now considering a transfer from/into a buffer alloced by freeRTOS's malloc I, as far I see, could land in both DTCM and RAM. Some online resources, e.g. ChibiOS forums, state that in case of SRAM the CortexM7 chaches must be invalidated or flushed for writes/reads accordingly and even the alignment against a cache line may need to be enforced. ChibiOS forum state that using DTCM only is a simple workaround, which according to manual does support DMA transfers.

So, as cache coherence problems may be nearly impossible to diagnose in the future, I'd ask in front: does (and if so - how?) the HAL ensure cache coherence in randomly allocated memory blocks? Do I need to modify the link script to work with DMA and possibly use DTCM more efficiently avoiding DMA collisions? Do I need to force a static buffer allocation instead of malloc?

Also, the refManual states that the DMA access to DTCM is done via a "specific AHB slave bus". Do I need to clock anything specific to enable it? (I'm fighting DMA Transfer errors currently and will post the code in an another thread if don't find the issue)

Best regards,
Mav

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