AnsweredAssumed Answered

ADC in dual interleaved mode in stm32f4 discovery

Question asked by kgb.georges on Oct 17, 2015
Latest reply on Nov 1, 2015 by UVWX
Hi, i have problem with determing number of cycles.
If i run ADC in dual interleaved mode with this parameters: 
ADC_TwoSamplingDelay_5Cycles + ADC_SampleTime_3Cycles with resolution 12b
on the first run of adc, data will be avaiable after 5 cycles, but on the second run after 10 cycles and so one ?
count cycles

Did adc need to end of conversion with the same interval of cycles ? If yes then what are correct values for 12 bit resolution with sample time equals 3 cycles to execute with maximum speed. In library directory STM32F4xx_StdPeriph_Examples there is example but for 8 bit resolution and 6 cycles of delay.