Hi, i have problem with determing number of cycles.

If i run ADC in dual interleaved mode with this parameters:

ADC_TwoSamplingDelay_5Cycles + ADC_SampleTime_3Cycles with resolution 12b

on the first run of adc, data will be avaiable after 5 cycles, but on the second run after 10 cycles and so one ?

count cycles

Did adc need to end of conversion with the same interval of cycles ? If yes then what are correct values for 12 bit resolution with sample time equals 3 cycles to execute with maximum speed. In library directory STM32F4xx_StdPeriph_Examples there is example but for 8 bit resolution and 6 cycles of delay.

If i run ADC in dual interleaved mode with this parameters:

ADC_TwoSamplingDelay_5Cycles + ADC_SampleTime_3Cycles with resolution 12b

on the first run of adc, data will be avaiable after 5 cycles, but on the second run after 10 cycles and so one ?

count cycles

Did adc need to end of conversion with the same interval of cycles ? If yes then what are correct values for 12 bit resolution with sample time equals 3 cycles to execute with maximum speed. In library directory STM32F4xx_StdPeriph_Examples there is example but for 8 bit resolution and 6 cycles of delay.

The alternate interpretation is that you get samples from each at 15 cycles, slewed by 5 cycles.

The way one can validate what's happening is to use DMA and time 100 or 1000 samples across the TC intervals. ie Toggle a GPIO in the TC Interrupt and scope it, or bench against a free running timer of know frequency.

I'm not big into the ADC, but when I don't understand how something works, or the manual is awkwardly presented, I go an test and validate my model of how it should work, with how it actually performs.

Hal might have some better insight.