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Embedded SRAM (Cache) Organization for STM32F429ZIT6U MCU

Question asked by imtiaz.sakib on Oct 16, 2015
Latest reply on Oct 16, 2015 by imtiaz.sakib

I am interested in knowing the physical memory organization for the embedded SRAM (cache) for the STM32F429ZIT6U core which is utilized in a STM32F429I-DISCOVERY Board.

The memory map within the global address space says that 192 KB of data can be accessed between addresses 0x20000000 => 0x20030000. I believe the memory is byte-addressable [32-bit address corresponds to 1-byte or 8-bits of data], and that the wordsize is 32-bits, since this MCU is based on the ARM Cortex M4. Is this all correct?

For e.g., is the memory organized as a matrix where each row contains 4 words, is the memory interleaved, is there any special aspect of the physical organization? I have the reference manual at hand, I wasn't able to find the cache organization. This is for the performing of running data analytics and statistics on the memory profile upon successive power-ons. Any help is sincerely appreciated.