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STM32 not restart after external Reset

Question asked by boeni.franz on Sep 7, 2015
Latest reply on Sep 14, 2015 by boeni.franz
Dear all
I use a master uP (STM32F072R8) and a slave uP (STM32F030K6) The slave processor is in AC main voltage and the main processor is  galavanic isolated from main voltage.
The main processor can reset the slave processor by a opto coupler. (see attachement)

The opto coupler can reset the slave processor. After power up the main processor hold the slave processor for 2s in Reset state. After this 2s starts slave also. This is the NRESET signal on Slave processor, when master processor starts the slave processor.

I tried:
- 47nF capacitor from NRST Pin to Minus of slave processor
- 10k pullup from NRST to 3.3V power supply of processor
- mechanical Reset Switch parallel to Opto Coupler

If master processor don't reset slave the slave processor start up allways. (Slave processor start up with rising power supply)
With mechanical Reset sometimes (30% of button clicks) the slave processor starts up.
With optocoupler (like schematic) slave processor never start up. Also pullup and/or 47nF capacitor don't help.
BOOT0 signal is perfect. I cannot see any spikes.
Power supply of slave CPU is also perfect. This voltage is provided by linear DCDC Converter NCP1117-3.3V.
For CPU schematic see attachement.

This is the SW for Clock initialisation:

 * SystemCoreClockConfigure: configure SystemCoreClock using HSI
                             (HSE is not populated on Discovery board)
void SystemCoreClockConfigure(void) {

  RCC->CR |= ((uint32_t)RCC_CR_HSION);                     // Enable HSI
  while ((RCC->CR & RCC_CR_HSIRDY) == 0);                  // Wait for HSI Ready

  RCC->CFGR = RCC_CFGR_SW_HSI;                             // HSI is system clock
  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);  // Wait for HSI used as system clock

  FLASH->ACR  = FLASH_ACR_PRFTBE;                          // Enable Prefetch Buffer
  FLASH->ACR |= FLASH_ACR_LATENCY;                         // Flash 1 wait state

  RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                         // HCLK = SYSCLK
  RCC->CFGR |= RCC_CFGR_PPRE_DIV1;                         // PCLK = HCLK

  RCC->CR &= ~RCC_CR_PLLON;                                // Disable PLL

  //  PLL configuration:  = HSI/2 * 12 = 48 MHz

  RCC->CR |= RCC_CR_PLLON;                                 // Enable PLL
  while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP();           // Wait till PLL is ready

  RCC->CFGR &= ~RCC_CFGR_SW;                               // Select PLL as system clock source
  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);  // Wait till PLL is system clock src

Hope somebody can help.

Best regards Franz