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Touch Sense (TSC) sawtooth problem

Question asked by hansen.niklas on Aug 28, 2015
Hi, I have a problem with the Touch Sense (TSC) module. No matter how I configure it and measure I always get a sawtooth wave added to it with an amplitude of a few percent of the total count. It seems to remain fairly constant in time with a period of about 80 seconds (haven't measured it exactly). I can't find any external sources for it nor internal. Even with all peripherals off except for TSC it's still present. If you turn of the TSC periodically and then after a while start to measure again you can see that the rise has been ongoing while the TSC has been disabled.
tscsawtooth.PNG

Here is my initializaion code for the TSC. When the acquisition is done I just read the value from TSC->IOGXCR and restart it after a delay (to allow for the capacitor to discharge properly).

-------------------------------------------------------------------------- tsc init code

  GPIO_InitTypeDef        GPIO_InitStructure;
  
  // turn on touch clock
  RCC->AHBENR |= RCC_AHBENR_TSEN;
  
  // setup io as af 3
  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
  GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_3);
  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_3);


  // channels and sheilds should be push pull
  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_0;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
  GPIO_Init(GPIOA, &GPIO_InitStructure);
  
  // sample should be open drain
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
  GPIO_Init(GPIOA, &GPIO_InitStructure);
  
  
  // interrupt enable 
  TSC->IER = 0x01;
  // int flag clear
  TSC->ICR = 0x03;


  // sampling
  TSC->IOSCR = (1 << 1);
  // channel
  TSC->IOCCR = 1;
  // enable the group
  TSC->IOGCSR = 1;

  
  union {
    uint32_t TSC_CR;
  struct {
        uint8_t TSCE    :1;
        uint8_t START   :1;
        uint8_t AM      :1;
        uint8_t SYNCPOL :1;
        uint8_t IODEF   :1;
        uint8_t MCV     :3;
        uint8_t unused  :4;
        uint8_t PGPSC   :3;
        uint8_t SSPSC   :1;
        uint8_t SSE     :1;
        uint8_t SSD     :7;
        uint8_t CTPL    :4;
        uint8_t CTPH    :4;
    } bits;
  } CR;
  
  CR.bits.CTPH = 0xf; // 16 clk high
  CR.bits.CTPL = 0xf; // 16 clk low
  CR.bits.SSD = 127;  // 127 spread
  CR.bits.SSE = 0;    // spread off
  CR.bits.SSPSC = 1;  // spread clk/2
  CR.bits.PGPSC = 0;  // pulse clk /0
  CR.bits.MCV = 6;    // max count 16383
  CR.bits.IODEF = 0;  // default low
  CR.bits.SYNCPOL = 0;// sync pol
  CR.bits.AM = 0;     // no sync
  CR.bits.START = 0;  // aquisition start
  CR.bits.TSCE = 1;   // module enable
  
  TSC->CR = CR.TSC_CR;
  
  // start
  TSC->CR |= 2;


-------------------------------------------------------------- end of code

Does anyone know what the problem might be?

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