AnsweredAssumed Answered

STM32F407VG Clock presclalers

Question asked by tikvic.marko on Aug 21, 2015
Latest reply on Aug 31, 2015 by waclawek.jan
Hello,

I have couple of questions and doubts about STM32F407VG MCU setup I would like to clarify a bit.

Q1: Do all the timers have the same clock source (system clock - PLL, HSI or HSE)? Because I have to divide APB1 and APB2 timers by 4 to get them to work on a same frequency as timers 6 and 7.  It's as if only timers 6 and 7 are affected by AHB prescaler.

Q2: Is there a known issues with PLL prescalers regarding the P divider? I have to set PLL_P bits to 0 and 1 (again division by 4) to get it to divide by 2 (not 4 as it should), because setting it to [0, 0] does nothing.

I believe the prescaling is off because I can get data over usart 2 with no problem, meaning I am calculating the BRR values correctly, meaning I am getting the frequency right, meaning some of the prescaling doesn't work as the reference manual says.

I would like some help about this, because I'm not sure anymore if I'm missing something obvious or if there really are problems.

Thank you,
Marko.

P.S.
I don't know if I should post code here, so here are links to my git repos.
PLL setup:
https://github.com/markotikvic/malgo-winhost/tree/master/src/clk.c
Uart setup:
https://github.com/markotikvic/malgo-winhost/tree/master/src/uart.c
Main:
https://github.com/markotikvic/malgo-winhost/tree/master/src/main.c

Outcomes