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DMA to TIM3 CCR1 problem!

Question asked by tjerneld.mikael on Aug 8, 2015
Latest reply on Aug 9, 2015 by tjerneld.mikael
Hi!  Device is STM32F103C8

A update event from TIM4 is used to trigger DMA channel7 who then is supposed to transfer 9 values in circular mode
to TIM3 CCR1. However the DMA transfers only one value and that one is set to 0 and  the rest is set to 127!?
So what i get is narrow pulse on CCR1 going round at the speed of  TIM4 update event.

1.#include "stm32f10x.h"
2.uint8_t buffer[9] = {0,16,32,48,64,80,96,112,127};


01.void tim4(void)
02.{
03./************************* Tim4  ****************************************************/
04.TIM4->CCMR1 |= 0b0110000001100000;  //OCM1 is set to PWM1 mode and OCM2 is set to PWM1 mode
05.TIM4->CCMR2 |= 0b0110000001100000;  //OCM3 is set to PWM1 mode and OCM4 is set to PWM1 mode
06.TIM4->CCER |= TIM_CCER_CC1E;      //Capture/Compare 1 output enable
07.TIM4->CCER |= TIM_CCER_CC2E;      //Capture/Compare 2 output enable
08.TIM4->CCER |= TIM_CCER_CC3E;      //Capture/Compare 1 output enable
09.TIM4->CCER |= TIM_CCER_CC4E;      //Capture/Compare 2 output enable
10.TIM4->PSC = 8192;             
11.TIM4->ARR = 1;                   
12.TIM4->CCR1 = 1;                   //CCR1 register set to initial PWM1 value
13.TIM4->CCR2 = 1;                   //CCR2 register set to initial PWM2 value
14.TIM4->CCR3 = 1;
15.TIM4->CCR4 = 1;
16.TIM4->DIER |= TIM_DIER_UDE;        //DMA request on tim4 Update event
17.TIM4->BDTR |= TIM_BDTR_MOE;      //Enable output stage
18.//TIM4->CR2 |= TIM_CR2_CCDS;       //DMA request on Update event
19.TIM4->CR1 |= TIM_CR1_CEN;         //Enable Timer4
20.}


01.void tim3(void)
02.{
03./************ Tim3  ********************************************************************/
04.TIM3->CCMR1 |= 0b0110000001100000;  //OCM1 is set to PWM1 mode and OCM2 is set to PWM1 mode
05.TIM3->CCMR2 |= 0b0110000001100000;  //OCM3 is set to PWM1 mode and OCM4 is set to PMW1 mode
06.TIM3->CCER |= TIM_CCER_CC1E;      //Capture/Compare 1 output enable
07.TIM3->CCER |= TIM_CCER_CC2E;      //Capture/Compare 2 output enable
08.TIM3->CCER |= TIM_CCER_CC3E;      //Capture/Compare 3 output enable
09.TIM3->CCER |= TIM_CCER_CC4E;      //Capture/Compare 4 output enable
10.TIM3->PSC = 0;                 
11.TIM3->ARR = 127;                
12.TIM3->CCR1 = 64;                  //CCR1 register set to initial PWM1 value
13.TIM3->CCR2 = 64;                  //CCR2 register set to initial PWM2 value
14.TIM3->CCR3 = 64;<br>
15.TIM3->CCR4 = 64;<br>
16.TIM3->BDTR |= TIM_BDTR_MOE;       //Enable output stage
17.TIM3->CR1 |= TIM_CR1_CEN;         //Enable Timer3
18.}



01.void dma1(void)
02.{
03./**************** DMA configuration......DMA ch7 triggered by TIM4 UD  ***********************************/
04.DMA1_Channel7->CCR = 0;                          //Reset CCR
05.DMA1->IFCR = 0;                                  //Clear all pending (old) DMA1 Stream's interrupts
06.DMA1_Channel7->CNDTR = 9;                        //Number of DMA transfers
07.DMA1_Channel7->CMAR |= (uint32_t)&buffer;        //Source, should fetch data from buffer!??!
08.DMA1_Channel7->CPAR |= (uint32_t)&(TIM3->CCR1);  //Destination, TIM3 CCR1
09.//DMA1_Channel7->CCR |= DMA_CCR7_PSIZE_0;   //Set peripheral size to 16bits
10.//DMA1_Channel7->CCR |= DMA_CCR7_MSIZE_0;   //Set memory size to 16bits
11.DMA1_Channel7->CCR |= DMA_CCR7_DIR;       //Read from memory to peripheral
12.DMA1_Channel7->CCR |= DMA_CCR7_MINC;      //Memory increment enabled
13.//DMA1_Channel7->CCR |= DMA_CCR7_MEM2MEM;   //Memory to memory enabled
14.//DMA1_Channel7->CCR |= DMA_CCR7_PINC;      //Peripheral increment enabled
15.DMA1_Channel7->CCR |= DMA_CCR7_CIRC;      //DMA set to circular mode
16.DMA1_Channel7->CCR |= DMA_CCR7_PL;        //Channel Priority level set to very high
17.DMA1_Channel7->CCR |= DMA_CCR7_EN;        //DMA channel7 enabled
18.}

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