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STMN32F407 TIM5 UIF interrupts

Question asked by san_filippo.will on Aug 5, 2015
Latest reply on Aug 6, 2015 by waclawek.jan
Hello:

I am using a stm32F407 and working on getting the timer overflow working correctly and I am seeing a strange thing. Basically, I seem to be getting two TIM5 interrupts for each overflow of the counter. Nothing really happens with the second interrupt as the UIF flag is cleared but I really dont want to get two interrupts. Do I need to clear the NVIC Pending flag for this interrupt for some reason? I did not think I needed to do that.

Here is a gdb dump of TIM5:
gdb) p {TIM_TypeDef}0x40000c00
$3 = {CR1 = 5, CR2 = 0, SMCR = 0, DIER = 1, SR = 0, EGR = 0, CCMR1 = 0, CCMR2 = 0, CCER = 0,
  CNT = 54834720, PSC = 83, ARR = 100000000, RCR = 0, CCR1 = 0, CCR2 = 0, CCR3 = 0, CCR4 = 0,
  BDTR = 0, DCR = 0, DMAR = 5, OR = 0}

NOTE: in the above example I have the ARR set to 100000000 but in my real code I set it to 0xFFFFFFFF as I just want to get an interrupt when the timer counter overflows. Same issue in both cases: tim5_isrs is always twice the uif_ints count.


Here is the interrupt handler I am using:


static voidtim5_isr(void){    uint32_t sr;    /* Count # of interrupts */    ++tim5_isrs;    sr = TIM5->SR;    if (sr & TIM_SR_UIF) {        ++uif_ints;    }    /* Clear the interrupt sources */    TIM5->SR &= ~sr;}
Thanks in advance to anyone that can help.

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