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STM32L4 ART Accelerator Data cache

Question asked by greg_stm on Jul 24, 2015
Latest reply on Aug 6, 2015 by Clive One
I understand the ART accelerator is designed to improve performance at high speeds (when FLASH wait states are nonzero)

But does the ART accelerator (in particular the Data cache) give any benefit if wait states are already zero, for example when the CPU runs at 4 MHz?

That is, if the code is straight-line with no looping or branching, does the Data cache help.

If it does, is there any document that gives more detailed information how to make best use of this feature (for optimising assembly language routines).