PISF: Periodic Interrupt Flag
This bit is set by hardware. It does not set when the RTC is running on battery. It is cleared by reading the register.
0: No periodic event
1: A periodic event occurred as configured by the PISEL bits in the RTC_CR register.
An interrupt is generated if the PIE bit in the RTC_CR register is set.
IRQStatus[15:0]: IRQ Status bits
These bits are set by hardware after masking by the VICx_INTER and VICx_INTSR
registers. An active bit will remain high until software clears the interrupt in the
registers of the peripheral which sourced the interrupt event. Each bit corresponds
to an input channel. IRQStatus0 gives the status of channel VICx.0 and
IRQStatus15 gives the status of channel VICx.15 (see Table 8.).
Retrieving data ...