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I'm Trying to Enable SDRAM without STM32 Library. But Not works.

Question asked by hong.yoon_ki on Jun 25, 2015
Latest reply on Jun 25, 2015 by Mark Edwards
Hi~ Every one!

I do not speak English well. Please note.

I am Trying to make open source Operating System for STM32F429 as a hobby. Introduce it simple. It is Intended for middle performance product. It will have scheduler, graphic library, device drive model. The using language is c++. The graphic library style using C++ is like Java. It will consist of Canvas, Panel, Button, etc, class. It is not use STM32 Library.

The Source code is here http://cafe.naver.com/rtboss/876. The project name is lss.

I'm Trying to Enable SDRAM without STM32 Library. But Not works. Please help me.

The Source code is below. (STM32F429-DISCOVERY Board)

int main(void)
{
    //PLL 144Mhz configuration. (It works correctly)
    setMcuRccHseEn(true);

    setMcuRccMainPllFactor(8, 288, 0, 3);
    setMcuRccMainPllSrc(true);
    setMcuRccMainPllOn(true);

    setMcuFlashLatency(4);
    setMcuFlashPrefetch(true);

    setMcuPwrVos(2);

    setMcuRccHpre(0);
    setMcuRccPpre2(4);
    setMcuRccPpre1(5);

    setMcuRccSysclkSw(RCC_CFGR_SW_PLL);

    // RCC GPIO (It works correctly)
    setMcuRccGpioBEn(true);
    setMcuRccGpioCEn(true);
    setMcuRccGpioDEn(true);
    setMcuRccGpioEEn(true);
    setMcuRccGpioFEn(true);
    setMcuRccGpioGEn(true);

    // SDRAM GPIO configuration. (It works correctly)
    setMcuGpioMode(GPIOB, 5, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOB, 6, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOC, 0, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 0, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 1, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 8, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 9, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 10, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 14, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOD, 15, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 0, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 1, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 7, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 8, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 9, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 10, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 11, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 12, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 13, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 14, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOE, 15, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 0, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 1, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 2, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 3, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 4, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 5, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 11, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 12, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 13, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 14, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOF, 15, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 0, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 1, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 4, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 5, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 8, GPIO_MODER_ALT_FUNC);
    setMcuGpioMode(GPIOG, 15, GPIO_MODER_ALT_FUNC);

    setMcuGpioAltfunc(GPIOB, 5, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOB, 6, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOC, 0, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 0, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 1, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 8, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 9, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 10, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 14, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOD, 15, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 0, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 1, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 7, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 8, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 9, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 10, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 11, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 12, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 13, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 14, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOE, 15, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 0, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 1, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 2, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 3, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 4, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 5, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 11, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 12, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 13, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 14, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOF, 15, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 0, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 1, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 4, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 5, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 8, GPIO_AFR_SDRAM);
    setMcuGpioAltfunc(GPIOG, 15, GPIO_AFR_SDRAM);

    setMcuGpioOspeed(GPIOB, 5, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOB, 6, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOC, 0, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 0, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 1, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 8, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 9, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 10, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 14, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOD, 15, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 0, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 1, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 7, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 8, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 9, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 10, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 11, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 12, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 13, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 14, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOE, 15, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 0, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 1, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 2, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 3, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 4, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 5, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 11, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 12, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 13, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 14, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOF, 15, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 0, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 1, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 4, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 5, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 8, GPIO_SPEED_FAST);
    setMcuGpioOspeed(GPIOG, 15, GPIO_SPEED_FAST);

    // RCC FMC configuration. (It works correctly)
    setMcuRccFmcEn(true);

    FmcSdramSdcr obj{
                        FMC_SDRAM_COL_ADDR_8BIT,
                        FMC_SDRAM_ROW_ADDR_12BIT,
                        FMC_SDRAM_DBUS_WIDTH_16BIT,
                        FMC_SDRAM_INT_BANK_FOUR,
                        3,
                        false,
                        2,
                        false,
                        FMC_SDRAM_RPIPE_1_HCLK_DELAY
                    };
   
    // SDCR configuration
    setMcuFmcSdramSdcr2(obj);

    // SDTR configuration
    setMcuFmcSdramTmrd(FMC_SDRAM_BANK2, 1);
    setMcuFmcSdramTxsr(FMC_SDRAM_BANK2, 4);
    setMcuFmcSdramTras(FMC_SDRAM_BANK2, 2);
    setMcuFmcSdramTrc(FMC_SDRAM_BANK1, 4); // BANK2 Don't care
    setMcuFmcSdramTwr(FMC_SDRAM_BANK2, 1);
    setMcuFmcSdramTrp(FMC_SDRAM_BANK1, 1); // BANK2 Don't care
    setMcuFmcSdramTrcd(FMC_SDRAM_BANK2, 1);

    waitMcuFmcSdramBusy();
   
    // Clock Configuration Enable
    setMcuFmcSdramCmd(0, 0, false, true, 1); // MRD, NRFS, BANK1, BANK2, MODE

    for(volatile unsigned long i=0;i<1000000;i++);

    // All Bank Precharge command
    waitMcuFmcSdramBusy();
    setMcuFmcSdramCmd(0, 0, false, true, 2); // MRD, NRFS, BANK1, BANK2, MODE

    // Auto-refresh command
    waitMcuFmcSdramBusy();
    setMcuFmcSdramCmd(0, 7, false, true, 3); // MRD, NRFS, BANK1, BANK2, MODE

    // Load Mode Register
    waitMcuFmcSdramBusy();
    buf = FMC_SDRAM_SDCMR_BURST_LENGTH_1
        | FMC_SDRAM_SDCMR_BURST_TYPE_SEQUENTIAL
        | FMC_SDRAM_SDCMR_CAS_LATENCY_3
        | FMC_SDRAM_SDCMR_OPERATING_MODE_STANDARD
        | FMC_SDRAM_SDCMR_WRITEBURST_MODE_SINGLE;

    setMcuFmcSdramCmd(buf, 0, false, true, 4); // MRD, NRFS, BANK1, BANK2, MODE

    // SDRTR configuration
    setMcuFmcSdramRtr(1386);

    waitMcuFmcSdramBusy();
   
    while(1)
    {
        // it monitoring code
        *(unsigned long*)(0xd0000000) = 0x12345678;
    }
}

inline void setMcuFmcSdramTrcd(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 24);
    buf |= (val << 24 & 0xFUL << 24);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTrp(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 20);
    buf |= (val << 20 & 0xFUL << 20);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTwr(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 16);
    buf |= (val << 16 & 0xFUL << 16);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTrc(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 12);
    buf |= (val << 12 & 0xFUL << 12);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTras(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 8);
    buf |= (val << 8 & 0xFUL << 8);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTxsr(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 4);
    buf |= (val << 4 & 0xFUL << 4);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramTmrd(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDTR[bank];
    buf &= ~(0xFUL << 0);
    buf |= (val << 0 & 0xFUL << 0);
    FMC_Bank5_6->SDTR[bank] = buf;
}

inline void setMcuFmcSdramRpipe(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 13);
    buf |= (val << 13 & 0x3UL << 13);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramRburstEn(unsigned char bank, bool val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(1UL << 12);
    buf |= (val << 12 & 1UL << 12);
    FMC_Bank5_6->SDCR[bank] = buf;
}


inline void setMcuFmcSdramSdclk(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 10);
    buf |= (val << 10 & 0x3UL << 10);
    FMC_Bank5_6->SDCR[bank] = buf;
}

struct FmcSdramSdcr
{
    unsigned nc : 2;
    unsigned nr : 2;
    unsigned mwid : 2;
    unsigned nb : 1;
    unsigned cas : 2;
    unsigned wp : 1;
    unsigned sdclk : 2;
    unsigned rburst : 1;
    unsigned rpipe : 2;
    unsigned rsv : 16;
};

inline void setMcuFmcSdramSdcr1(FmcSdramSdcr obj)
{
    unsigned long *buf = (unsigned long*)(&obj);
    FMC_Bank5_6->SDCR[0] = *buf;
}

inline void setMcuFmcSdramSdcr2(FmcSdramSdcr obj)
{
    unsigned long lsdcr = FMC_Bank5_6->SDCR[0];
    unsigned long *psdcr = (unsigned long*)(&obj);
    FmcSdramSdcr *ssdcr = (FmcSdramSdcr*)(&lsdcr);

    lsdcr &= ~(0x7fffUL);
    ssdcr->rburst = obj.rburst;
    ssdcr->rpipe = obj.rpipe;
    ssdcr->sdclk = obj.sdclk;
   
    FMC_Bank5_6->SDCR[0] = lsdcr;
    FMC_Bank5_6->SDCR[1] = *psdcr;
}

inline void setMcuFmcSdramWp(unsigned char bank, bool val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(1UL << 9);
    buf |= (val << 9 & 1UL << 9);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramCas(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 7);
    buf |= (val << 7 & 0x3UL << 7);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramNb(unsigned char bank, bool val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(1UL << 6);
    buf |= (val << 6 & 1UL << 6);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramMwid(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 4);
    buf |= (val << 4 & 0x3UL << 4);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramNr(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 2);
    buf |= (val << 2 & 0x3UL << 2);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void setMcuFmcSdramNc(unsigned char bank, unsigned char val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDCR[bank];
    buf &= ~(0x3UL << 0);
    buf |= (val << 0 & 0x3UL << 0);
    FMC_Bank5_6->SDCR[bank] = buf;
}

inline void waitMcuFmcSdramBusy(void)
{
    while(FMC_Bank5_6->SDSR & (1 << 5));
}

inline void setMcuFmcSdramCmd(unsigned short mrd, unsigned char nrfs, bool ctb1, bool ctb2, unsigned char mode)
{
    FMC_Bank5_6->SDCMR = (mrd << 9 & 0x1FFFUL << 9) | (nrfs << 5 & 0xFUL << 5) | (ctb1 << 4) | (ctb2 << 3) | mode & 0x7UL;
}

inline void setMcuFmcSdramRtr(unsigned short val)
{
    unsigned long buf;
   
    buf = FMC_Bank5_6->SDRTR;
    buf &= ~(0xFFFUL << 1);
    buf |= (val << 1 & 0xFFFUL << 1);
    FMC_Bank5_6->SDRTR = buf;
}

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