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STM32F030 TIM1 trigger ADC1 (no HAL)

Question asked by haertl.sebastian.001 on Jun 23, 2015

I am using a STM32F030-µC to control a brushless DC-Motor and i want to trigger the ADC with the TIM1. Channel 4 of the TIM1 (CC4) is programmed to look after a compare-event and the ADC should use this event to start the conversion (TRG1: TRG_CC4). Actually i have the problem that the ADC doesnt start any conversion. I read a lot of discussions but almost all developers are using the HAL-Library. However at the current state of development i dont want to use any HALs, so i masked the registers with defines from the device header. In some posts, there was the chronological order a problem. I compared the instructions of the HAL-Library with my code and adapted it. The problem is the same..
Below are the Code, especially the Init-Functions

Can anybody help me?
Best regards

int main (void)
{   
    // System
    SetSystemClock();
    SysTickTimer_Init();
      
    // Peripherie
    GPIO_Init();
    TIM1_Init();
    ADC_Init();
      
    // Start Peripherie
    TIM1_SetCOM();      
  
    while (1)
    {
          
    }
}// END
  
void TIM1_Init (void)
{
    // Timer1 clock
    TIM1_ClockEnable();
      
    // Clock Prescal-Counter: CLK_CNT = 48/2 = 24 MHz
    TIM1->PSC = 0x0001;
      
    // PWM - Frequency : 10kHz
    TIM1->ARR = 2399;
      
    // Duty-Cycle
    TIM1->CCR1 = 1199;                                  // DutyCycle 50%
    TIM1->CCR2 = 1199;                                  //    -- " --
    TIM1->CCR3 = 1199;                                  //    -- " --
    TIM1->CCR4 = (TIM1->ARR)/2;                 //AD-Trigger
      
    // Configuration
    TIM1->CR1   &=~ TIM_CR1_DIR;                // upcounting mdoe
    TIM1->CR1       &=~ TIM_CR1_CMS;                // Edge-aligned mode
    TIM1->CR1       &=~ TIM_CR1_CKD;                
    TIM1->CR1       &=~ TIM_CR1_OPM;                
    TIM1->CR1       &=~ TIM_CR1_URS;                
    TIM1->CR1       &=~ TIM_CR1_UDIS;               // Update enabled
      
    TIM1->CR2       &=~ TIM_CR2_OIS1;               
    TIM1->CR2       &=~ TIM_CR2_OIS1N;          
    TIM1->CR2       &=~ TIM_CR2_OIS2;               
    TIM1->CR2       &=~ TIM_CR2_OIS2N;          
    TIM1->CR2       &=~ TIM_CR2_OIS3;               
    TIM1->CR2       &=~ TIM_CR2_OIS3N;          
    TIM1->CR2   &=~ TIM_CR2_OIS4;               
    TIM1->CR2       &=~ TIM_CR2_CCUS;               
    TIM1->CR2       |=  TIM_CR2_CCPC;               
                                                                              
      
    TIM1->CCMR1 |=  TIM_CCMR1_OC1PE;        // OC1 preload enable
    TIM1->CCMR1 |=  TIM_CCMR1_OC1M_1        // PWM-Mode 1 (Left-aligned)
                    |     TIM_CCMR1_OC1M_2;     //        --- " ----
    TIM1->CCMR1 |=  TIM_CCMR1_OC2PE;        
    TIM1->CCMR1 |=  TIM_CCMR1_OC2M_1        
                            |   TIM_CCMR1_OC2M_2;       
    TIM1->CCMR2 |=  TIM_CCMR2_OC3PE;        
    TIM1->CCMR2 |=  TIM_CCMR2_OC3M_1        
                            |   TIM_CCMR2_OC3M_2;       
    TIM1->CCMR2 &=~ TIM_CCMR2_CC4S;         
    TIM1->CCMR2 |=  TIM_CCMR2_OC4PE;        
    TIM1->CCMR2 &=~ TIM_CCMR2_OC4M;         // OC4 Frozen
                                                                                                      
    TIM1->CCER  |=  TIM_CCER_CC1E;          // Capture/Compare Channel 1 enable
    TIM1->CCER  &=~ TIM_CCER_CC1P;          // Channel 1 active high
    TIM1->CCER  |=  TIM_CCER_CC1NE;         
    TIM1->CCER  &=~ TIM_CCER_CC1NP;         
    TIM1->CCER  |=  TIM_CCER_CC2E;          
    TIM1->CCER  &=~ TIM_CCER_CC2P;          
    TIM1->CCER  |=  TIM_CCER_CC2NE;         
    TIM1->CCER  &=~ TIM_CCER_CC2NP;         
    TIM1->CCER  |=  TIM_CCER_CC3E;          
    TIM1->CCER  &=~ TIM_CCER_CC3P;          
    TIM1->CCER  |=  TIM_CCER_CC3NE;         
    TIM1->CCER  &=~ TIM_CCER_CC3NP;         
    TIM1->CCER  |=  TIM_CCER_CC4E;          
    TIM1->CCER  &=~ TIM_CCER_CC4P;          
      
    TIM1->BDTR |=  TIM_BDTR_OSSR;               
    TIM1->BDTR &=~ TIM_BDTR_OSSI;               
    TIM1->BDTR &=~ TIM_BDTR_DTG;                
    TIM1->BDTR |=  TIM_BDTR_DTG_4               
                         |   TIM_BDTR_DTG_5;            
                           
    // Start TIM1                    
    TIM1_Start();
      
    // Master Output enable
    TIM1->BDTR |=  TIM_BDTR_MOE;                // Master Output enable
      
}// END
  
void ADC_Init(void)
{   
    // ADC Clock Mode
    ADC1->CFGR2     &=~ ADC_CFGR2_CKMODE;       // ADCCLK Asynchronous Clock= 14MHz
      
    ADC_ClockEnable();
          
    ADC1->IER       |=  ADC_IER_EOCIE;          
    ADC1->CFGR1     &=~ ADC_CFGR1_DISCEN;       
    ADC1->CFGR1     &=~ ADC_CFGR1_AUTOFF;       
    ADC1->CFGR1     &=~ ADC_CFGR1_WAIT;         
    ADC1->CFGR1     &=~ ADC_CFGR1_CONT;         // Single conversion mode
    ADC1->CFGR1     |=  ADC_CFGR1_OVRMOD;       
    ADC1->CFGR1     &=~ ADC_CFGR1_ALIGN;        // Right alignment
    ADC1->CFGR1     &=~ ADC_CFGR1_RES;          //  12-Bit
    ADC1->CFGR1     &=~ ADC_CFGR1_SCANDIR;  // Scan Ch0 -> Ch17
    ADC1->CFGR1     &=~ ADC_CFGR1_DMAEN;        // DMA disabled
    ADC1->CFGR1   |=  ADC_CFGR1_EXTEN_0;    // Hardware-Trigger rising edge
    ADC1->CFGR1   |=  ADC_CFGR1_EXTSEL_0;    // Trigge TRG1: TIM1_CC4
      
    ADC1->SMPR      &=~ ADC_SMPR_SMP;               // 1.5 ADC-clock cycles sample time
      
    ADC1->CHSELR    |=  ADC_CHSELR_CHSEL9;
  
    // Interrupt
    IRQ_ADC_Init();
      
    // ADC-Calibration
    ADC1->CR |= ADC_CR_ADCAL;
    while ((ADC1->CR & ADC_CR_ADCAL) == ADC_CR_ADCAL)   
    {}
      
    // ADC enable
    ADC1->CR = ADC_CR_ADEN;
    // wait for  AD-Ready
    while ((ADC1->ISR & ADC_ISR_ADRDY)==0)
    {}
      
    ADC_Start();
      
}// END

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