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Worst case delay from DMA request to transfer in stm32f103RBT6

Question asked by STM32_learner on Jun 18, 2015
Latest reply on Jun 18, 2015 by waclawek.jan
I have a DMA channel configured to transfer data from memory to GPIOC->ODR on a PWM1 channel's CC event. This same PWM1 channel is used to read the data output on GPIOC by an FPGA. A falling edge triggers a request to the DMA channel, and a falling edge signals the FPGA to read the data from the port. I'm looking to maximize the frequency of this signal while at the same time insuring that the relevant data is read only after the DMA transfer has happened. 

Is 200ns from request to transfer a good value?