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ADC Common Status Register

Question asked by gardner.jerry on Jun 12, 2015
Latest reply on Jun 15, 2015 by Clive One
The STM32F429 has three ADCs: ADC1, ADC2, and ADC3. They all have a status register, which has an EOC bit to indicate conversion complete.

There's also a common status register (ADC_CSR) shared by all three ADCs that contains copies of the status bits of all three ADCs.

When I start an ADC conversion on ADC1, it completes, and I see the EOC bit set in ADC1_SR, but EOC1 does not get set in ADC_CSR.

Since all three ADCs share a common interrupt, I'm using the common status register to determine which ADC caused the interrupt by checking which EOCx bit is set, but it's not working because the EOCx bits are not getting set when their corresponding EOC bit is set in the ADCx_SR registers.

I checked the STM32F429 errata, but see no mention of this. Is there something I need to do to get the EOCx bits to accurately reflect the state of the EOC bits in ADCx_SR?