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Question asked by White.John on May 30, 2015
Latest reply on Jun 1, 2015 by waclawek.jan
I an laying down some decode logic for 2 x 16 bit SRAMs using Chip Select NE1, by bus configured for 32 bits 12 address lines.
If I Write using address 0x60000000 the NBL0 and NBL1 signals are both low during the NE1 cycle.
If the address is odd i.e. A0 = 1 NBL0 and NBL1 produce 2 seperate pulses NBL1 at the begining of the NE1 cycle returning hign and then NBL1 goes low returning high at the end of the NE1 cycle.
This seems to make sense as write pulse occur during the 2 NBL cycles as explaine by Table 263 Ref Manual.
I do not understand why this is not produced when the Address is odd, A0 = 1.
My silicon is Rev 1 as I understand that some devices have had problems with FMC.

Any help would be appreciated.

Rds John W