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SPI controller on Slave generate RXNE interrupt before last bit was received

Question asked by schnitzler.stefan on May 26, 2015
Latest reply on Jun 8, 2015 by waclawek.jan
Hello,
I want to realize a SPI master slave communication with an STM32F0 Microcontroller. My SPI master use the following configuration:
- Most Significant Bit first
- 8 Bits per Transfer
- Clock is Low when inactive (CPOL = 0)
- Data is Valid on Clock Leading Edge (CPHA = 0)
- Enable Line is Active Low

The SPI frame is 32 bit long. The first transmit byte contains the address and the information if it is an read / write request. I use the CMSIS Libary to configure the SPI controller. In order to capture the first byte I setup my slave as follow:

  SPI_InitTypeDef SPI_InitStructure;
  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
   /* clock to zero when idle */
   SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
   /* The first clock transition is the first data caputure edge */
   SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
   /* TODO: EAC requirements, SPI speed Master mode is 3MHz */
   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
   SPI_InitStructure.SPI_NSS  = SPI_NSS_Hard;
   SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
   SPI_I2S_DeInit(CTRL_SPIx);

   SPI_Init(CTRL_SPIx, &SPI_InitStructure);

   NVIC_EnableIRQ(SPIx_IRQn);
/* Configures the FIFO reception threshold to
    * generate an RXNE interrupt request event if the FIFO
    * level is greater or equal to 1/4.
    */
   SPI_RxFIFOThresholdConfig (CTRL_SPIx, SPI_RxFIFOThreshold_QF );

   /* Enable the TXE and RXNE interrupt */
   SPI_I2S_ITConfig (CTRL_SPIx, SPI_I2S_IT_TXE,  DISABLE);
   SPI_I2S_ITConfig (CTRL_SPIx, SPI_I2S_IT_RXNE, ENABLE);
   SPI_I2S_ITConfig (CTRL_SPIx, SPI_I2S_IT_ERR,  DISABLE);

   /* Enable the SPI peripheral */
   SPI_Cmd(CTRL_SPIx, ENABLE);

In my SPI interrupt I do the following thinks:
  if (CTRL_SPIx->SR & SPI_I2S_FLAG_RXNE)
   {
      uint16_t rx=0;

      DB_PIN1_SET();
      rx = CTRL_SPIx->DR;

      CTRL_SPIx->DR = 0xAA;

      SPI_I2S_ClearFlag  ( CTRL_SPIx,   SPI_I2S_FLAG_RXNE );

      DB_PIN1_RESET();
   }
   else
   {
      SPI_I2S_ClearFlag  ( CTRL_SPIx,   SPI_I2S_FLAG_TXE );
      SPI_I2S_ClearFlag  ( CTRL_SPIx,   SPI_I2S_FLAG_BSY );
      SPI_I2S_ClearFlag  ( CTRL_SPIx,   SPI_I2S_FLAG_OVR );
   }
When I stopped the Processor in the SPI Interrupt the SPI Controller has the following configuration:
CR1: 0x50
CR2: 0x1740
SR: 0x483
DR: 0x0
CRCPR: 0x2
RXCRCR: 0x0
TXCRCR: 0x0
I2SCFGR: 0x0
ISPR: 0x2

The attached file shows the SPI communication. DEBUG_PIN1 is set when enter the SPI interrupt and reset before leave the SPI interrupt.

Thank you every body for your support.

Best regards,

Stefan.

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