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system clock configuration issue in stm32f407vg

Question asked by tag.aseok on May 25, 2015
Latest reply on May 25, 2015 by Clive One
Suppose configuring system clock to 168MHz.
According to page 226 of RM0090_Rev9, it is recommended to set PLLM in a way to achieve 2MHz for VCO input frequency(e.g. 8MHz HSE with PLLM=4) in order to limit jitter and PLLN(between 192 and 432) must be set such that VCO output frequency(VCO input frequency times PLLN) doesn't exceed 432 MHz, but this two configuration will conflict.
How to solve this issue?

168 = 2 * (PLLN/PLLP) ==> PLLN=84*PLLP
PLLP>=2(e.g. 4) ==> PLLN=336 ==> (PLLN * VCO_input) = 672(not allowed)