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STM32F411xx flash latency discrepancy

Question asked by hind.russell on Apr 21, 2015
Latest reply on Apr 22, 2015 by waclawek.jan
The reference manaul for the STM32F411 series says that for a CPU running at 100MHz on a 2.7-3.6 supply voltage, the flash latency should be 3 wait cycles. 

However, the CMSIS startup file (system_stm32f4xx.c v1.5.0 dated 06-March-2015) provided with v1.5 of the std periph driver set it to 2 wait cycles:

  /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

But the comments at the top of the file for STM32F411xx series agrees with the reference manual that the latency should be 3WS.  Is this a bug in the CMSIS file or a non-documented optimisation for this processor?