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DMA request queue

Question asked by Luke on Apr 9, 2015
Latest reply on Apr 9, 2015 by Luke
Hi all,
I am working on an STM32F0 project in which I am triggering a DMA transfer using peripheral events such as an input capture. Looking over the docs it seems a little vague as to the behaviour of the DMA controller in response to events that occur whilst a DMA transfer is currently in progress on the same channel. In my particular scenario I am initiating a DMA transfer using an input capture on the first edge of a GPIO. On the first edge, a set number of bits are transferred from the port. Since the capture and data signal are on the same line, the capture event should trigger only a single DMA transfer for a specified number of clock ticks, then be immediately ready for another trigger as soon as the transfer is complete. Since there will generally be multiple edge triggers during data transfer they should obviously not interfere with the behavior of the DMA transfer in progress.

My confusion is regarding how the DMA controller behaves when it receives these extra DMA events while it is already servicing a DMA transfer on that channel - will it simply ignore them, or is there some sort of queue system per channel that will lead to additional transfers after the first is complete? The manual seems to indicate there might be some sort of queue going on: 
"If there are more requests, the peripheral can initiate the next transaction."
Presuming this is true, what is its behavior (i.e. is it a simple counter) and can it be controlled in software?