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ptp initialisation on stm32F407

Question asked by de_kruijf.jan on Mar 23, 2015

Hallo,
Regarding STM32F407ZGT6 controller chip on an Olimex stm32-e407 board.

I have a problem with initializing the fine adjustment for the PTP block
The TSARU bit does not return to 0 after setting it.
I wonder if someone might throw some light on this.

Here is the sequence of operations:
-----------------------------------

reset the board,
download the flash image
continuous step to breakpoint just before the problem
and then single step thru the problem zone.

also running the board without the debugger attached gives a hung board
in the ptp init area.


Here is an abbreviated program listing (from start up):
------------------------------------------------------
(the registers are loaded in a temp reg and the bits are set as needed
then temp registers are written back. This is to help reading the prog. and avoid partial writes)

  ( Reset_Registers  -- reset bits: Off, Reset, Off )


-- select media interface for ETH
      PMC_Tmp.MII_RMII_SEL    := Scfg.RMII;
-- write to hardware
      R.Syscfg.PMC            := PMC_Tmp;


-- start some clocks:

      Ahb1en_Tmp.GPIOA     := Rcc.Enable;  -- for eth_rmii interface pins
      Ahb1en_Tmp.GPIOB     := Rcc.Enable;  --
      Ahb1en_Tmp.GPIOC     := Rcc.Enable;  -- for eth_rmii interface pins
      Ahb1en_Tmp.GPIOG     := Rcc.Enable;  -- for eth_rmii interface pins
-- write to hardware
      R.Rcc.AHB1ENR        := Ahb1en_Tmp;


     ( Init_Pins        -- amonst others for the ETH block )

-- start the ptp clock
      Ahb1en_Tmp.ETHMACPTP := Rcc.Enable;
      R.Rcc.AHB1ENR        := Ahb1en_Tmp;


( init usart 6, incl. dma)

      Finrod.Board.Init_Eth_Clock; -- positioned this in various places
                                   -- but it has to be before the PTP control
                                   -- register gets updated (apparently)


-- no interrupts
      Macimr_Tmp.TSTIM       := Eth.Int_Disabled;
      R.Eth_Mac.Macimr       := Macimr_Tmp; -- write it
      
-- enable time stamping
      Ptpt_Control_Tmp.Tse        := Eth.Enabled;
      Ptpt_Control_Tmp.TSSIPV4FE  := Eth.Enabled;
      Ptpt_Control_Tmp.TSSARFE    := Eth.Enabled;
      Ptpt_Control_Tmp.TSPTPPSV2E := Eth.Enabled;
      Ptpt_Control_Tmp.Tsaru := Eth.Off; -- for the unfathomable reason
                                         -- this might work

      R.Eth_Mac.PTPTSCR      := Ptpt_Control_Tmp; -- write it

( small delay loop)

      PTP_SSIR_Tmp.Stssi     := 43;
      R.Eth_Mac.PTPSSIR      := PTP_SSIR_Tmp;  -- write it;

      R.Eth_Mac.PTPTSAR      := 3_652_183_076; -- write it directly, its 32 bits
      
      -- update it, and wait for it to be done
      Ptpt_Control_Tmp.Tsaru := Eth.Update;
      R.Eth_Mac.PTPTSCR      := Ptpt_Control_Tmp; -- write it

      while Ptpt_Control_Tmp.Tsaru /= Eth.Off loop
     Ptpt_Control_Tmp    := R.Eth_Mac.PTPTSCR;
      end loop;
 
And this loop never ends  . . . . . . .
I have attached a pdf with the debugger output of the registers affected, at the time of the endless loop.

I did cross check against the hardware errata and against the CMSIS library.

Regards,

Jan de Kruyf.

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