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FMC SRAM High Speed problem

Question asked by pollack.brandon on Mar 6, 2015
Latest reply on Mar 10, 2015 by jacquet.aaron
I'm using Keil on an stm32f4xx with 10ns read/write sram

I have configured the FMC with a data ready of 2 HCLK (my speed is 180 Mhz) so that is 90 Mhz, which is slower than the rating of 100 Mhz of the SRAM, however the FMC will not read/write the sram correctly unless it is set to a data ready delay of 3 instead of 2 (60 Mhz)

I have enabled the compensation cell and set all GPIO clocks associated with the FMC to high, what could cause this?

The speed isnt high enough for length matching to be an issue, nor should the Z0 cause a problem (it is around 60 Ohms, close enough to 50), any tips?