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SWD clock restrictions

Question asked by Uwe Bonnes on Mar 6, 2015
Latest reply on Mar 6, 2015 by Clive One

the STM32 datasheets do not mention any restictions on SWD or JTAG frequency. Some "internet knowledge" tells that older ARM cores had a HCLK/6 limitation on SWD/JTAG clock frequency. Has anybody hard facts for Cortex-M and/or STM32?