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DMA Returned Array organization STM32f051K4TX

Question asked by Trash Hammer on Feb 26, 2015
Latest reply on Feb 26, 2015 by Trash Hammer
I looked at several post and discovered that other have seen the following:

Thanks again for your reply. The code is working fine. 
It seems like the data in the array is arranged like this:
RegularConvData[0];  // PA7
RegularConvData[1];  // PA4
RegularConvData[2];  // PA5
RegularConvData[3];  // PA6

I am doing a very similar project with ADC transfers of ADC_Channel0 and ADC_Channel1.  I also used the internal Vbat, Vtemp and Vref channels as a reference in data alignment and understand.

Can some explain the nature of the ADC data alignment in the returned DMA transfer array?

It seems to be unrelated to the channel.  I am seeing ADC channels 0 and 1 in positions 0 and 4 of the array respectively.

I expected to see 
Channel0
Channel1
Channel16
Channel17
Channle18

I am seeing the array come back as

Channel0
Channel??
Channel??
Channel??
Channel1

The Channel?? are 16,17 and 18 but I do not recall the order currently.  I have been searching for a answer in the reference manual and memory addresses for several hours an still have no idea how the DMA array order is created.











                                                   
           
Thanks again for your reply. The code is working fine. 
            It seems like the data in the array is arranged like this:
RegularConvData[0];  // PA7
RegularConvData[1];  // PA4
RegularConvData[2];  // PA5
RegularConvData[3];  // PA6

           

           
                                                   
           
Thanks again for your reply. The code is working fine. 
            It seems like the data in the array is arranged like this:
           
RegularConvData[0];  // PA7
RegularConvData[1];  // PA4
RegularConvData[2];  // PA5
RegularConvData[3];  // PA6

           
           
           

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