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SPI with mixed DMA / manual XFER and TXFIFO issue

Question asked by helton.gregory.002 on Feb 15, 2015
Latest reply on Mar 9, 2015 by Reh.Tilmann.001
I am using SPI in slave mode with a mix of manual transmission/reception at the beginning of my message protocol (first 3 bytes manual), then DMA in the middle for the data transfer, then manual ACK/NAK byte response at the end based on the received CRC.

The first message goes through and slave code responds exactly as expected. However, when the master sends the second message, the first byte in response sent by the slave is incorrect, and the other response bytes are skewed/delayed by 1 byte. It appears as if the TXFIFO has an extra byte in it (that I didn't load, or didn't intentionally load), and this byte is sent before my "good" data.

Setting a breakpoint at the beginning of the routine, I can see that the setup for SPI and DMA are identical for the first message which works, and second message that does not work.

After I finish a message, I would like to clear the transmit and receive FIFOs to get a fresh start. Clearing the receive FIFO is not a problem (just read SPI1->DR four times and discard the results). Is there a way to clear the TXFIFO, or at least reset the internal TXFIFO pointer ?

It is strange that I would have to do this at all since there shouldn't be any "extra" bytes in the TXFIFO anyway. Everything that I've loaded has been sent -  no less - no more.  I waited unit the DMA indicated that the transfer was complete, and that the BSY flag was set, indicating the last DMA byte was in flight, before the last manual byte was sent. A screen capture of my Total Phase Cheetah log is attached. The format is 

Master Sent/Slave Sent

The first message is good. The slave response to the master 81 is AA. However, in the second message, when the master sends 81, the slave sends 15. I have no idea where this came from. I searched in memory in the areas close to the DMA buffer, but could not find it.

Any help or insight would be appreciated.