AnsweredAssumed Answered

Running STM32 without crystal

Question asked by risetech on Feb 9, 2015
Latest reply on Feb 9, 2015 by Clive One
Hi,

I'm trying to run STM32F103ZET6 with the internal clock source (HSI). According to datasheet it should be possible up to 64 MHz. Right now I have the following system_stm32f10x.c file from the examples, and it uses the crystal to get 72 MHz. I tried to change

996.RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);

to

996.RCC->CFGR |= (uint32_t)(0 | RCC_CFGR_PLLMULL8); // 8 MHz HSI * 8 = 64 MHz?

but I got 8 Mhz not 64. What do I need to change in this file to get 64 MHz (or 72 would be even better if possible) with HSI? Thank you very much...

0001./**
0002.  ******************************************************************************
0003.  * @file    GPIO/IOToggle/system_stm32f10x.c
0004.  * @author  MCD Application Team
0005.  * @version V3.4.0
0006.  * @date    10/15/2010
0007.  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
0008.  ****************************************************************************** 
0009.  *
0010.  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
0011.  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
0012.  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
0013.  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
0014.  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
0015.  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
0016.  *
0017.  * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
0018.  ******************************************************************************
0019.  */
0020. 
0021./** @addtogroup CMSIS
0022.  * @{
0023.  */
0024. 
0025./** @addtogroup stm32f10x_system
0026.  * @{
0027.  */ 
0028.   
0029./** @addtogroup STM32F10x_System_Private_Includes
0030.  * @{
0031.  */
0032. 
0033.#include "stm32f10x.h"
0034. 
0035./**
0036.  * @}
0037.  */
0038. 
0039./** @addtogroup STM32F10x_System_Private_TypesDefinitions
0040.  * @{
0041.  */
0042. 
0043./**
0044.  * @}
0045.  */
0046. 
0047./** @addtogroup STM32F10x_System_Private_Defines
0048.  * @{
0049.  */
0050. 
0051./*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
0052.   frequency (after reset the HSI is used as SYSCLK source)
0053.    
0054.   IMPORTANT NOTE:
0055.   ==============
0056.   1. After each device reset the HSI is used as System clock source.
0057. 
0058.   2. Please make sure that the selected System clock doesn't exceed your device's
0059.      maximum frequency.
0060.       
0061.   3. If none of the define below is enabled, the HSI is used as System clock
0062.    source.
0063. 
0064.   4. The System clock configuration functions provided within this file assume that:
0065.        - For Low, Medium and High density Value line devices an external 8MHz
0066.          crystal is used to drive the System clock.
0067.        - For Low, Medium and High density devices an external 8MHz crystal is
0068.          used to drive the System clock.
0069.        - For Connectivity line devices an external 25MHz crystal is used to drive
0070.          the System clock.
0071.     If you are using different crystal you have to adapt those functions accordingly.
0072.    */
0073.     
0074.#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
0075./* #define SYSCLK_FREQ_HSE    HSE_VALUE */
0076.//#define SYSCLK_FREQ_24MHz  24000000
0077.#else
0078./* #define SYSCLK_FREQ_HSE    HSE_VALUE */
0079./* #define SYSCLK_FREQ_24MHz  24000000 */
0080./* #define SYSCLK_FREQ_36MHz  36000000 */
0081./* #define SYSCLK_FREQ_48MHz  48000000 */
0082./* #define SYSCLK_FREQ_56MHz  56000000 */
0083.#define SYSCLK_FREQ_72MHz  72000000
0084.#endif
0085. 
0086./*!< Uncomment the following line if you need to use external SRAM mounted
0087.     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
0088.     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
0089.#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
0090./* #define DATA_IN_ExtSRAM */
0091.#endif
0092. 
0093./*!< Uncomment the following line if you need to relocate your vector Table in
0094.     Internal SRAM. */
0095./* #define VECT_TAB_SRAM */
0096.#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
0097.                                  This value must be a multiple of 0x100. */
0098. 
0099. 
0100./**
0101.  * @}
0102.  */
0103. 
0104./** @addtogroup STM32F10x_System_Private_Macros
0105.  * @{
0106.  */
0107. 
0108./**
0109.  * @}
0110.  */
0111. 
0112./** @addtogroup STM32F10x_System_Private_Variables
0113.  * @{
0114.  */
0115. 
0116./*******************************************************************************
0117.*  Clock Definitions
0118.*******************************************************************************/
0119.#ifdef SYSCLK_FREQ_HSE
0120.  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
0121.#elif defined SYSCLK_FREQ_24MHz
0122.  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
0123.#elif defined SYSCLK_FREQ_36MHz
0124.  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
0125.#elif defined SYSCLK_FREQ_48MHz
0126.  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
0127.#elif defined SYSCLK_FREQ_56MHz
0128.  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
0129.#elif defined SYSCLK_FREQ_72MHz
0130.  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
0131.#else /*!< HSI Selected as System Clock source */
0132.  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
0133.#endif
0134. 
0135.__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
0136./**
0137.  * @}
0138.  */
0139. 
0140./** @addtogroup STM32F10x_System_Private_FunctionPrototypes
0141.  * @{
0142.  */
0143. 
0144.static void SetSysClock(void);
0145. 
0146.#ifdef SYSCLK_FREQ_HSE
0147.  static void SetSysClockToHSE(void);
0148.#elif defined SYSCLK_FREQ_24MHz
0149.  static void SetSysClockTo24(void);
0150.#elif defined SYSCLK_FREQ_36MHz
0151.  static void SetSysClockTo36(void);
0152.#elif defined SYSCLK_FREQ_48MHz
0153.  static void SetSysClockTo48(void);
0154.#elif defined SYSCLK_FREQ_56MHz
0155.  static void SetSysClockTo56(void); 
0156.#elif defined SYSCLK_FREQ_72MHz
0157.  static void SetSysClockTo72(void);
0158.#endif
0159. 
0160.#ifdef DATA_IN_ExtSRAM
0161.  static void SystemInit_ExtMemCtl(void);
0162.#endif /* DATA_IN_ExtSRAM */
0163. 
0164./**
0165.  * @}
0166.  */
0167. 
0168./** @addtogroup STM32F10x_System_Private_Functions
0169.  * @{
0170.  */
0171. 
0172./**
0173.  * @brief  Setup the microcontroller system
0174.  *         Initialize the Embedded Flash Interface, the PLL and update the
0175.  *         SystemCoreClock variable.
0176.  * @note   This function should be used only after reset.
0177.  * @param  None
0178.  * @retval None
0179.  */
0180.void SystemInit (void)
0181.{
0182.  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
0183.  /* Set HSION bit */
0184.  RCC->CR |= (uint32_t)0x00000001;
0185. 
0186.  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
0187.#ifndef STM32F10X_CL
0188.  RCC->CFGR &= (uint32_t)0xF8FF0000;
0189.#else
0190.  RCC->CFGR &= (uint32_t)0xF0FF0000;
0191.#endif /* STM32F10X_CL */  
0192.   
0193.  /* Reset HSEON, CSSON and PLLON bits */
0194.  RCC->CR &= (uint32_t)0xFEF6FFFF;
0195. 
0196.  /* Reset HSEBYP bit */
0197.  RCC->CR &= (uint32_t)0xFFFBFFFF;
0198. 
0199.  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
0200.    RCC->CFGR &= (uint32_t)0xFF80FFFF;
0201.    //RCC->CFGR &= (uint32_t)0xFFBCFFFF; // use HSI/2 as PLLSRC, PLLMUL = 16 for a SYSCLK of 64 MHz (max with HSI)
0202.     
0203.#ifdef STM32F10X_CL
0204.  /* Reset PLL2ON and PLL3ON bits */
0205.  RCC->CR &= (uint32_t)0xEBFFFFFF;
0206. 
0207.  /* Disable all interrupts and clear pending bits  */
0208.  RCC->CIR = 0x00FF0000;
0209. 
0210.  /* Reset CFGR2 register */
0211.  RCC->CFGR2 = 0x00000000;
0212.#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
0213.  /* Disable all interrupts and clear pending bits  */
0214.  RCC->CIR = 0x009F0000;
0215. 
0216.  /* Reset CFGR2 register */
0217.  RCC->CFGR2 = 0x00000000;     
0218.#else
0219.  /* Disable all interrupts and clear pending bits  */
0220.  RCC->CIR = 0x009F0000;
0221.#endif /* STM32F10X_CL */
0222.     
0223.#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
0224.  #ifdef DATA_IN_ExtSRAM
0225.    SystemInit_ExtMemCtl();
0226.  #endif /* DATA_IN_ExtSRAM */
0227.#endif
0228. 
0229.  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
0230.  /* Configure the Flash Latency cycles and enable prefetch buffer */
0231.  SetSysClock();
0232. 
0233.#ifdef VECT_TAB_SRAM
0234.  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
0235.#else
0236.  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
0237.#endif
0238.}
0239. 
0240./**
0241.  * @brief  Update SystemCoreClock according to Clock Register Values
0242.  * @note   None
0243.  * @param  None
0244.  * @retval None
0245.  */
0246.void SystemCoreClockUpdate (void)
0247.{
0248.  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
0249. 
0250.#ifdef  STM32F10X_CL
0251.  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
0252.#endif /* STM32F10X_CL */
0253. 
0254.#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
0255.  uint32_t prediv1factor = 0;
0256.#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
0257.     
0258.  /* Get SYSCLK source -------------------------------------------------------*/
0259.  tmp = RCC->CFGR & RCC_CFGR_SWS;
0260.   
0261.  switch (tmp)
0262.  {
0263.    case 0x00:  /* HSI used as system clock */
0264.      SystemCoreClock = HSI_VALUE;
0265.      break;
0266.    case 0x04:  /* HSE used as system clock */
0267.      SystemCoreClock = HSE_VALUE;
0268.      break;
0269.    case 0x08:  /* PLL used as system clock */
0270. 
0271.      /* Get PLL clock source and multiplication factor ----------------------*/
0272.      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
0273.      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
0274.       
0275.#ifndef STM32F10X_CL     
0276.      pllmull = ( pllmull >> 18) + 2;
0277.       
0278.      if (pllsource == 0x00)
0279.      {
0280.        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
0281.        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
0282.      }
0283.      else
0284.      {
0285. #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
0286.       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
0287.       /* HSE oscillator clock selected as PREDIV1 clock entry */
0288.       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
0289. #else
0290.        /* HSE selected as PLL clock entry */
0291.        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
0292.        {/* HSE oscillator clock divided by 2 */
0293.          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
0294.        }
0295.        else
0296.        {
0297.          SystemCoreClock = HSE_VALUE * pllmull;
0298.        }
0299. #endif
0300.      }
0301.#else
0302.      pllmull = pllmull >> 18;
0303.       
0304.      if (pllmull != 0x0D)
0305.      {
0306.         pllmull += 2;
0307.      }
0308.      else
0309.      { /* PLL multiplication factor = PLL input clock * 6.5 */
0310.        pllmull = 13 / 2;
0311.      }
0312.             
0313.      if (pllsource == 0x00)
0314.      {
0315.        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
0316.        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
0317.      }
0318.      else
0319.      {/* PREDIV1 selected as PLL clock entry */
0320.         
0321.        /* Get PREDIV1 clock source and division factor */
0322.        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
0323.        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
0324.         
0325.        if (prediv1source == 0)
0326.        {
0327.          /* HSE oscillator clock selected as PREDIV1 clock entry */
0328.          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;         
0329.        }
0330.        else
0331.        {/* PLL2 clock selected as PREDIV1 clock entry */
0332.           
0333.          /* Get PREDIV2 division factor and PLL2 multiplication factor */
0334.          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
0335.          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
0336.          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                        
0337.        }
0338.      }
0339.#endif /* STM32F10X_CL */
0340.      break;
0341. 
0342.    default:
0343.      SystemCoreClock = HSI_VALUE;
0344.      break;
0345.  }
0346.   
0347.  /* Compute HCLK clock frequency ----------------*/
0348.  /* Get HCLK prescaler */
0349.  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
0350.  /* HCLK clock frequency */
0351.  SystemCoreClock >>= tmp; 
0352.}
0353. 
0354./**
0355.  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
0356.  * @param  None
0357.  * @retval None
0358.  */
0359.static void SetSysClock(void)
0360.{
0361.#ifdef SYSCLK_FREQ_HSE
0362.  SetSysClockToHSE();
0363.#elif defined SYSCLK_FREQ_24MHz
0364.  SetSysClockTo24();
0365.#elif defined SYSCLK_FREQ_36MHz
0366.  SetSysClockTo36();
0367.#elif defined SYSCLK_FREQ_48MHz
0368.  SetSysClockTo48();
0369.#elif defined SYSCLK_FREQ_56MHz
0370.  SetSysClockTo56(); 
0371.#elif defined SYSCLK_FREQ_72MHz
0372.  SetSysClockTo72();
0373.#endif
0374.  
0375. /* If none of the define above is enabled, the HSI is used as System clock
0376.    source (default after reset) */
0377.}
0378. 
0379./**
0380.  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s
0381.  *          before jump to __main
0382.  * @param  None
0383.  * @retval None
0384.  */
0385.#ifdef DATA_IN_ExtSRAM
0386./**
0387.  * @brief  Setup the external memory controller.
0388.  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
0389.  *           This function configures the external SRAM mounted on STM3210E-EVAL
0390.  *         board (STM32 High density devices). This SRAM will be used as program
0391.  *         data memory (including heap and stack).
0392.  * @param  None
0393.  * @retval None
0394.  */
0395.void SystemInit_ExtMemCtl(void)
0396.{
0397./*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
0398.  required, then adjust the Register Addresses */
0399. 
0400.  /* Enable FSMC clock */
0401.  RCC->AHBENR = 0x00000114;
0402.   
0403.  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ 
0404.  RCC->APB2ENR = 0x000001E0;
0405.   
0406./* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
0407./*----------------  SRAM Address lines configuration -------------------------*/
0408./*----------------  NOE and NWE configuration --------------------------------*/ 
0409./*----------------  NE3 configuration ----------------------------------------*/
0410./*----------------  NBL0, NBL1 configuration ---------------------------------*/
0411.   
0412.  GPIOD->CRL = 0x44BB44BB; 
0413.  GPIOD->CRH = 0xBBBBBBBB;
0414. 
0415.  GPIOE->CRL = 0xB44444BB; 
0416.  GPIOE->CRH = 0xBBBBBBBB;
0417. 
0418.  GPIOF->CRL = 0x44BBBBBB; 
0419.  GPIOF->CRH = 0xBBBB4444;
0420. 
0421.  GPIOG->CRL = 0x44BBBBBB; 
0422.  GPIOG->CRH = 0x44444B44;
0423.    
0424./*----------------  FSMC Configuration ---------------------------------------*/ 
0425./*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
0426.   
0427.  FSMC_Bank1->BTCR[4] = 0x00001011;
0428.  FSMC_Bank1->BTCR[5] = 0x00000200;
0429.}
0430.#endif /* DATA_IN_ExtSRAM */
0431. 
0432.#ifdef SYSCLK_FREQ_HSE
0433./**
0434.  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
0435.  *          and PCLK1 prescalers.
0436.  * @note   This function should be used only after reset.
0437.  * @param  None
0438.  * @retval None
0439.  */
0440.static void SetSysClockToHSE(void)
0441.{
0442.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0443.   
0444.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
0445.  /* Enable HSE */   
0446.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0447.  
0448.  /* Wait till HSE is ready and if Time out is reached exit */
0449.  do
0450.  {
0451.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0452.    StartUpCounter++; 
0453.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0454. 
0455.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0456.  {
0457.    HSEStatus = (uint32_t)0x01;
0458.  }
0459.  else
0460.  {
0461.    HSEStatus = (uint32_t)0x00;
0462.  
0463. 
0464.  if (HSEStatus == (uint32_t)0x01)
0465.  {
0466. 
0467.#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
0468.    /* Enable Prefetch Buffer */
0469.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0470. 
0471.    /* Flash 0 wait state */
0472.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0473. 
0474.#ifndef STM32F10X_CL
0475.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
0476.#else
0477.    if (HSE_VALUE <= 24000000)
0478.    {
0479.      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
0480.    }
0481.    else
0482.    {
0483.      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
0484.    }
0485.#endif /* STM32F10X_CL */
0486.#endif
0487.  
0488.    /* HCLK = SYSCLK */
0489.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0490.       
0491.    /* PCLK2 = HCLK */
0492.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0493.     
0494.    /* PCLK1 = HCLK */
0495.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
0496.     
0497.    /* Select HSE as system clock source */
0498.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0499.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;   
0500. 
0501.    /* Wait till HSE is used as system clock source */
0502.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
0503.    {
0504.    }
0505.  }
0506.  else
0507.  { /* If HSE fails to start-up, the application will have wrong clock
0508.         configuration. User can add here some code to deal with this error */
0509.  
0510.}
0511.#elif defined SYSCLK_FREQ_24MHz
0512./**
0513.  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
0514.  *          and PCLK1 prescalers.
0515.  * @note   This function should be used only after reset.
0516.  * @param  None
0517.  * @retval None
0518.  */
0519.static void SetSysClockTo24(void)
0520.{
0521.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0522.   
0523.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
0524.  /* Enable HSE */   
0525.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0526.  
0527.  /* Wait till HSE is ready and if Time out is reached exit */
0528.  do
0529.  {
0530.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0531.    StartUpCounter++; 
0532.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0533. 
0534.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0535.  {
0536.    HSEStatus = (uint32_t)0x01;
0537.  }
0538.  else
0539.  {
0540.    HSEStatus = (uint32_t)0x00;
0541.  
0542. 
0543.  if (HSEStatus == (uint32_t)0x01)
0544.  {
0545.#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
0546.    /* Enable Prefetch Buffer */
0547.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0548. 
0549.    /* Flash 0 wait state */
0550.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0551.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;   
0552.#endif
0553.  
0554.    /* HCLK = SYSCLK */
0555.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0556.       
0557.    /* PCLK2 = HCLK */
0558.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0559.     
0560.    /* PCLK1 = HCLK */
0561.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
0562.     
0563.#ifdef STM32F10X_CL
0564.    /* Configure PLLs ------------------------------------------------------*/
0565.    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
0566.    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
0567.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
0568.                            RCC_CFGR_PLLMULL6);
0569. 
0570.    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
0571.    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */      
0572.    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
0573.                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
0574.    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
0575.                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
0576.   
0577.    /* Enable PLL2 */
0578.    RCC->CR |= RCC_CR_PLL2ON;
0579.    /* Wait till PLL2 is ready */
0580.    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
0581.    {
0582.    }  
0583.#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
0584.    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
0585.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
0586.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
0587.#else   
0588.    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
0589.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
0590.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
0591.#endif /* STM32F10X_CL */
0592. 
0593.    /* Enable PLL */
0594.    RCC->CR |= RCC_CR_PLLON;
0595. 
0596.    /* Wait till PLL is ready */
0597.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
0598.    {
0599.    }
0600. 
0601.    /* Select PLL as system clock source */
0602.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0603.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
0604. 
0605.    /* Wait till PLL is used as system clock source */
0606.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0607.    {
0608.    }
0609.  }
0610.  else
0611.  { /* If HSE fails to start-up, the application will have wrong clock
0612.         configuration. User can add here some code to deal with this error */
0613.  }
0614.}
0615.#elif defined SYSCLK_FREQ_36MHz
0616./**
0617.  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
0618.  *          and PCLK1 prescalers.
0619.  * @note   This function should be used only after reset.
0620.  * @param  None
0621.  * @retval None
0622.  */
0623.static void SetSysClockTo36(void)
0624.{
0625.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0626.   
0627.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
0628.  /* Enable HSE */   
0629.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0630.  
0631.  /* Wait till HSE is ready and if Time out is reached exit */
0632.  do
0633.  {
0634.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0635.    StartUpCounter++; 
0636.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0637. 
0638.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0639.  {
0640.    HSEStatus = (uint32_t)0x01;
0641.  }
0642.  else
0643.  {
0644.    HSEStatus = (uint32_t)0x00;
0645.  
0646. 
0647.  if (HSEStatus == (uint32_t)0x01)
0648.  {
0649.    /* Enable Prefetch Buffer */
0650.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0651. 
0652.    /* Flash 1 wait state */
0653.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0654.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;   
0655.  
0656.    /* HCLK = SYSCLK */
0657.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0658.       
0659.    /* PCLK2 = HCLK */
0660.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0661.     
0662.    /* PCLK1 = HCLK */
0663.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
0664.     
0665.#ifdef STM32F10X_CL
0666.    /* Configure PLLs ------------------------------------------------------*/
0667.     
0668.    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
0669.    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
0670.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
0671.                            RCC_CFGR_PLLMULL9);
0672. 
0673.    /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
0674.    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
0675.         
0676.    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
0677.                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
0678.    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
0679.                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
0680.   
0681.    /* Enable PLL2 */
0682.    RCC->CR |= RCC_CR_PLL2ON;
0683.    /* Wait till PLL2 is ready */
0684.    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
0685.    {
0686.    }
0687.     
0688.#else   
0689.    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
0690.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
0691.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
0692.#endif /* STM32F10X_CL */
0693. 
0694.    /* Enable PLL */
0695.    RCC->CR |= RCC_CR_PLLON;
0696. 
0697.    /* Wait till PLL is ready */
0698.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
0699.    {
0700.    }
0701. 
0702.    /* Select PLL as system clock source */
0703.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0704.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
0705. 
0706.    /* Wait till PLL is used as system clock source */
0707.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0708.    {
0709.    }
0710.  }
0711.  else
0712.  { /* If HSE fails to start-up, the application will have wrong clock
0713.         configuration. User can add here some code to deal with this error */
0714.  }
0715.}
0716.#elif defined SYSCLK_FREQ_48MHz
0717./**
0718.  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
0719.  *          and PCLK1 prescalers.
0720.  * @note   This function should be used only after reset.
0721.  * @param  None
0722.  * @retval None
0723.  */
0724.static void SetSysClockTo48(void)
0725.{
0726.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0727.   
0728.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
0729.  /* Enable HSE */   
0730.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0731.  
0732.  /* Wait till HSE is ready and if Time out is reached exit */
0733.  do
0734.  {
0735.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0736.    StartUpCounter++; 
0737.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0738. 
0739.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0740.  {
0741.    HSEStatus = (uint32_t)0x01;
0742.  }
0743.  else
0744.  {
0745.    HSEStatus = (uint32_t)0x00;
0746.  
0747. 
0748.  if (HSEStatus == (uint32_t)0x01)
0749.  {
0750.    /* Enable Prefetch Buffer */
0751.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0752. 
0753.    /* Flash 1 wait state */
0754.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0755.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;   
0756.  
0757.    /* HCLK = SYSCLK */
0758.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0759.       
0760.    /* PCLK2 = HCLK */
0761.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0762.     
0763.    /* PCLK1 = HCLK */
0764.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
0765.     
0766.#ifdef STM32F10X_CL
0767.    /* Configure PLLs ------------------------------------------------------*/
0768.    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
0769.    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
0770.         
0771.    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
0772.                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
0773.    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
0774.                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
0775.   
0776.    /* Enable PLL2 */
0777.    RCC->CR |= RCC_CR_PLL2ON;
0778.    /* Wait till PLL2 is ready */
0779.    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
0780.    {
0781.    }
0782.     
0783.    
0784.    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
0785.    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
0786.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
0787.                            RCC_CFGR_PLLMULL6);
0788.#else   
0789.    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
0790.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
0791.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
0792.#endif /* STM32F10X_CL */
0793. 
0794.    /* Enable PLL */
0795.    RCC->CR |= RCC_CR_PLLON;
0796. 
0797.    /* Wait till PLL is ready */
0798.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
0799.    {
0800.    }
0801. 
0802.    /* Select PLL as system clock source */
0803.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0804.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
0805. 
0806.    /* Wait till PLL is used as system clock source */
0807.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0808.    {
0809.    }
0810.  }
0811.  else
0812.  { /* If HSE fails to start-up, the application will have wrong clock
0813.         configuration. User can add here some code to deal with this error */
0814.  }
0815.}
0816. 
0817.#elif defined SYSCLK_FREQ_56MHz
0818./**
0819.  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
0820.  *          and PCLK1 prescalers.
0821.  * @note   This function should be used only after reset.
0822.  * @param  None
0823.  * @retval None
0824.  */
0825.static void SetSysClockTo56(void)
0826.{
0827.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0828.   
0829.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/  
0830.  /* Enable HSE */   
0831.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0832.  
0833.  /* Wait till HSE is ready and if Time out is reached exit */
0834.  do
0835.  {
0836.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0837.    StartUpCounter++; 
0838.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0839. 
0840.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0841.  {
0842.    HSEStatus = (uint32_t)0x01;
0843.  }
0844.  else
0845.  {
0846.    HSEStatus = (uint32_t)0x00;
0847.  
0848. 
0849.  if (HSEStatus == (uint32_t)0x01)
0850.  {
0851.    /* Enable Prefetch Buffer */
0852.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0853. 
0854.    /* Flash 2 wait state */
0855.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0856.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;   
0857.  
0858.    /* HCLK = SYSCLK */
0859.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0860.       
0861.    /* PCLK2 = HCLK */
0862.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0863.     
0864.    /* PCLK1 = HCLK */
0865.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
0866. 
0867.#ifdef STM32F10X_CL
0868.    /* Configure PLLs ------------------------------------------------------*/
0869.    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
0870.    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
0871.         
0872.    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
0873.                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
0874.    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
0875.                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
0876.   
0877.    /* Enable PLL2 */
0878.    RCC->CR |= RCC_CR_PLL2ON;
0879.    /* Wait till PLL2 is ready */
0880.    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
0881.    {
0882.    }
0883.     
0884.    
0885.    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
0886.    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
0887.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
0888.                            RCC_CFGR_PLLMULL7);
0889.#else    
0890.    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
0891.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
0892.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
0893. 
0894.#endif /* STM32F10X_CL */
0895. 
0896.    /* Enable PLL */
0897.    RCC->CR |= RCC_CR_PLLON;
0898. 
0899.    /* Wait till PLL is ready */
0900.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
0901.    {
0902.    }
0903. 
0904.    /* Select PLL as system clock source */
0905.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0906.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
0907. 
0908.    /* Wait till PLL is used as system clock source */
0909.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0910.    {
0911.    }
0912.  }
0913.  else
0914.  { /* If HSE fails to start-up, the application will have wrong clock
0915.         configuration. User can add here some code to deal with this error */
0916.  }
0917.}
0918. 
0919.#elif defined SYSCLK_FREQ_72MHz
0920./**
0921.  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
0922.  *          and PCLK1 prescalers.
0923.  * @note   This function should be used only after reset.
0924.  * @param  None
0925.  * @retval None
0926.  */
0927.static void SetSysClockTo72(void)
0928.{
0929.  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
0930.   
0931.  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
0932.  /* Enable HSE */   
0933.  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
0934.  
0935.  /* Wait till HSE is ready and if Time out is reached exit */
0936.  do
0937.  {
0938.    HSEStatus = RCC->CR & RCC_CR_HSERDY;
0939.    StartUpCounter++; 
0940.  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
0941. 
0942.  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
0943.  {
0944.    HSEStatus = (uint32_t)0x01;
0945.  }
0946.  else
0947.  {
0948.    HSEStatus = (uint32_t)0x00;
0949.  
0950. 
0951.  if (HSEStatus == (uint32_t)0x01)
0952.  {
0953.    /* Enable Prefetch Buffer */
0954.    FLASH->ACR |= FLASH_ACR_PRFTBE;
0955. 
0956.    /* Flash 2 wait state */
0957.    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
0958.    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;   
0959. 
0960.  
0961.    /* HCLK = SYSCLK */
0962.    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
0963.       
0964.    /* PCLK2 = HCLK */
0965.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
0966.     
0967.    /* PCLK1 = HCLK */
0968.    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
0969. 
0970.#ifdef STM32F10X_CL
0971.    /* Configure PLLs ------------------------------------------------------*/
0972.    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
0973.    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
0974.         
0975.    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
0976.                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
0977.    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
0978.                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
0979.   
0980.    /* Enable PLL2 */
0981.    RCC->CR |= RCC_CR_PLL2ON;
0982.    /* Wait till PLL2 is ready */
0983.    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
0984.    {
0985.    }
0986.     
0987.    
0988.    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
0989.    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
0990.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
0991.                            RCC_CFGR_PLLMULL9);
0992.#else   
0993.    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
0994.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
0995.                                        RCC_CFGR_PLLMULL));
0996.    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
0997.#endif /* STM32F10X_CL */
0998. 
0999.    /* Enable PLL */
1000.    RCC->CR |= RCC_CR_PLLON;
1001. 
1002.    /* Wait till PLL is ready */
1003.    while((RCC->CR & RCC_CR_PLLRDY) == 0)
1004.    {
1005.    }
1006.     
1007.    /* Select PLL as system clock source */
1008.    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
1009.    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
1010. 
1011.    /* Wait till PLL is used as system clock source */
1012.    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
1013.    {
1014.    }
1015.  }
1016.  else
1017.  { /* If HSE fails to start-up, the application will have wrong clock
1018.         configuration. User can add here some code to deal with this error */
1019.  }
1020.}
1021.#endif
1022. 
1023./**
1024.  * @}
1025.  */
1026. 
1027./**
1028.  * @}
1029.  */
1030.   
1031./**
1032.  * @}
1033.  */   
1034./******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

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