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STM32 TIM2 ARR requires 32-bit access

Question asked by Dan Hepler on Feb 5, 2015
Latest reply on Feb 5, 2015 by Dan Hepler
Hello, I found some unexpected behaviour with the 32-bit TIM2 module on STM32F4xx devices, and many others.

When accessing the TIM2->ARR (a 32-bit timer) register, 16-bit writes have the following behaviour.  If you try writing 0x0987 to TIM2->ARR, it will actually write 0x09870987.  The high and low half-words have been written with this value.

I found this behaviour using a DMA transfer, but the problem is much more basic and can be reproduced easily single-stepping through some code.

01.#include "stm32f4xx.h"
02. 
03.int main(void)
04.{
05.  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
06. 
07.  /* 32-bit writes to TIM2->ARR work fine */
08.  uint32_t *pARR_32 = (uint32_t *)&TIM2->ARR;
09.  *pARR_32 = 0x00000123;
10. 
11.  /* 16-bit writes to TIM2->ARR DO NOT WORK AS EXPECTED*/
12.  uint16_t *pARR_16 = (uint16_t *)&TIM2->ARR;
13.  *pARR_16 = 0x0987;
14.  if( TIM2->ARR == 0x09870987 )
15.  {
16.    while(1); // FAILED: High and low half-words are repeated
17.  }
18.   
19.  while(1); // Does not make it here
20.}

As JW posted below (thanks!), this behaviour is both expected and documented.  Hope this helps someone else who may not have realized it.

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