Hi there,

I'm having difficulties understanding how to use the PTP hardware clock that is integrated

in many STM32 devices with MAC Peripheral. The STM32F4x7 reference manual contains a diagram

of the clock on page 1142, which seems to be built off two feedback accumulators. I'm following

up with a list of my understandings.

a) Both feedback loops run at clock HCLK.

b) The upper "addend loop" can overflow every [0...(2e32-1)/2e32 = approx 1] HCLK clocks, adding the value 1 to the subseconds register if that happens in a clock period.

c) The lower "constant loop" adds the value "constant" to the subseconds register every HCLK.

d) The subseconds register contains the elapsed Nanoseconds (0 ... 10e9-1)

e) The "constant" values supposed meaning is "Nanoseconds per HCLK", which is a rational number.

f) Since the "constant" value must be an integer, I have to round the rational number, and since the "addend loop" can only move the clock forward, more precisely I have to floor the rational number.

g) floor( rational ) - rational gives me the fractional number of nanoseconds the "lower loop" runs slow every HCLK.

h) I could also redefine the meaning of the subsecond and second registers, so they represent the true time scaled by any constant > 1. Is this normal usage?

Following from my understanding, on a 168MHz clock, I would use "constant" = floor( 1000MHz/168MHz ) = floor( 5.9524 ) = 5. This would lead to the clock running slow 0.9524 nanoseconds per HCLK, which I have to compensate with the upper "addend loop". Now 0.9524 is very close to the maximum the "addend loop" can compensate for, which makes me at least curious, but it is workable. Following from h) I could also redefine the meaning of the time registers to mean 10 * time, thus representing the time in 100 picosecond increments. Leaving the error at 0.5 (* 100 picoseconds) per HCLK, "releaving" the "addend loop" limits, but introducing a scaling in the client code (so factors of 2^N would be favourable, but that does not seem to work well with the overflowing of the subsecond register into the seconds register).

Now that being said, that does not seem to be correct in any way.

Following the diagram in the reference manual, it is stated that "The system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy" which I cannot make any sense off.

Also in the application note AN3411 "IEEE 1588 precision time protocol demonstration

for STM32F107 connectivity line microcontroller", page 10 introduces a value "tick" which I don't understand. On the following page 11 sample values are given in a table. The last row mentions a tick value of "14ns", which comes close to the (1000MHz/72MHz) I would calculate for the unscaled "constant loop" register, however it is rounded up and also used during calculation, which leaves me puzzled about what behaviour the calculated constants shall create.

It would be really great if anyone could spot my various misconceptions.

Kind regards

I'm having difficulties understanding how to use the PTP hardware clock that is integrated

in many STM32 devices with MAC Peripheral. The STM32F4x7 reference manual contains a diagram

of the clock on page 1142, which seems to be built off two feedback accumulators. I'm following

up with a list of my understandings.

a) Both feedback loops run at clock HCLK.

b) The upper "addend loop" can overflow every [0...(2e32-1)/2e32 = approx 1] HCLK clocks, adding the value 1 to the subseconds register if that happens in a clock period.

c) The lower "constant loop" adds the value "constant" to the subseconds register every HCLK.

d) The subseconds register contains the elapsed Nanoseconds (0 ... 10e9-1)

e) The "constant" values supposed meaning is "Nanoseconds per HCLK", which is a rational number.

f) Since the "constant" value must be an integer, I have to round the rational number, and since the "addend loop" can only move the clock forward, more precisely I have to floor the rational number.

g) floor( rational ) - rational gives me the fractional number of nanoseconds the "lower loop" runs slow every HCLK.

h) I could also redefine the meaning of the subsecond and second registers, so they represent the true time scaled by any constant > 1. Is this normal usage?

Following from my understanding, on a 168MHz clock, I would use "constant" = floor( 1000MHz/168MHz ) = floor( 5.9524 ) = 5. This would lead to the clock running slow 0.9524 nanoseconds per HCLK, which I have to compensate with the upper "addend loop". Now 0.9524 is very close to the maximum the "addend loop" can compensate for, which makes me at least curious, but it is workable. Following from h) I could also redefine the meaning of the time registers to mean 10 * time, thus representing the time in 100 picosecond increments. Leaving the error at 0.5 (* 100 picoseconds) per HCLK, "releaving" the "addend loop" limits, but introducing a scaling in the client code (so factors of 2^N would be favourable, but that does not seem to work well with the overflowing of the subsecond register into the seconds register).

Now that being said, that does not seem to be correct in any way.

Following the diagram in the reference manual, it is stated that "The system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy" which I cannot make any sense off.

Also in the application note AN3411 "IEEE 1588 precision time protocol demonstration

for STM32F107 connectivity line microcontroller", page 10 introduces a value "tick" which I don't understand. On the following page 11 sample values are given in a table. The last row mentions a tick value of "14ns", which comes close to the (1000MHz/72MHz) I would calculate for the unscaled "constant loop" register, however it is rounded up and also used during calculation, which leaves me puzzled about what behaviour the calculated constants shall create.

It would be really great if anyone could spot my various misconceptions.

Kind regards